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Datasheet File OCR Text:

Bt860/861
Multiport YCrCb to NTSC / PAL / SECAM Digital Video Encoder
The Bt860/861 is a multiport digital video encoder with pixel synchronization and per-pixel blending capabilities. The three 8-bit YCrCb data ports allow for a variety of video and graphic overlay configurations useful in video set-top box applications. The Bt860/861 is specifically designed for video systems requiring composite, Y/C (S-Video), and simultaneous component YUV or RGB (SCART) video signals. Worldwide video standards are supported, including NTSC-M (N. America, Taiwan, Japan), PAL-B,D,G,H,I (Europe, Asia), PAL-M (Brazil), PAL-N (Uruguay, Paraguay), PAL-Nc (Argentina), PAL-60, NTSC-443, and SECAM. The Bt860 and Bt861 are functionally identical except that the Bt861 can output the Macrovision 7.x anticopy algorithm. Multisource video is a key feature of the Bt860/861. Two general purpose ports (P and OSD) allow synchronization with sources that can share clock and frame timing control with the Bt860/861, such as digital video and graphic overlay content generated by an MPEG video decoder. A third port (VID) is specifically configured to interface with video decoders such as those in the Conexant VideoStream decoder family. Any pair of these three ports can be synchronized and blended.
Distinguishing Features
* * Six 10-bit DACs with individual power management Simultaneous output of YUV, S-Video, and CVBS, or RGB (SCART), S-Video, and CVBS Current drive output DACs for superior video quality and reduced system cost Dynamic video load sensing for reduced power operation Three sharpness filter options (1,2,3.5 dB gain) and four reduction filter options Programmable adjustment of brightness, contrast, color saturation, and hue Glueless interface with a video decoder Three 8-bit YCrCb 4:2:2 inputs for overlay or blending ITU-R BT.656, ITU-R BT.601 digital video input options NTSC-M, PAL (B,D,G,H,I), PAL-M, PAL-N, NTSC-443, PAL-Nc, PAL-60 and SECAM video output 2x upsampling and internal filtering for reduced cost Master or slave video timing with programmable HSYNC* delay Interlaced/noninterlaced operation Macrovision 7.x copy protection (Bt861) Closed Captioning and Extended Data Services encoding Teletext encoding (WST system B) 400 kHz serial programming interface On-board voltage reference Reduced power modes Programmable luma delay (two channels) 3.3 V supply, 5 V-tolerant inputs Copy Generation Management System (CGMS) support VARIS-II and Wide Screen Signalling (WSS) multiple aspect ratio support Internal color bar generation Blue field generation 80-pin MQFP package Bt852, Bt868/869, Bt864A/865A, Bt866/867 Bt835, Bt829A/B Digital cable television systems Satellite TV receivers (DBS/DVB/DSS) DVD players Video CD players Digital cameras PC add-on cards Video editing
* * * * * * * *
* * * * *
Functional Block Diagram
RESET* SID SIC ALTADDR VREF FSADJ1
TTXDAT TTXREQ VID[7:0] VIDCLK VIDHACT VIDVACT VIDVALID VIDFIELD HSYNC* VSYNC* BLANK* FIELD ALPHA[1:0] P[7:0] OSD[7:0] CLKO XTI XTO CLKIN
Teletext Encoder
Serial Interface
Internal VREF 10
COMP1
DAC
DAC A
* * * * * * * * * * * * * * * * * * * *
10
DAC
DAC B
10 Pixel Sync. and Mixing 2x Upsampling Mod. and Mixer
DAC
DAC C
10
DAC
DAC D
1.3 MHz LPF
Color Space Convert
10
Related Products
DAC DAC E DAC DAC F
10
Applications
XTAL OSC PLL Clock Generation Internal VREF COMP2
FSADJ2
Data Sheet
D860DSA July 27, 1999
Ordering Information
Model Number BT860KRF Bt861KRF Package 80-Pin MQFP 80-Pin MQFP Operating Temperature 0 C-70 C 0 C-70 C
Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without notice. Conexant products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Conexant product can reasonably be expected to result in personal injury or death. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. Conexant and "What's Next in Communications Technologies" are trademarks of Conexant Systems, Inc. This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other intellectural property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovison and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. (c) 1999 Conexant Systems, Inc. Printed in U.S.A. All Rights Reserved
Reader Response: To improve the quality of our publications, we welcome your feedback. Please send comments or suggestions via e-mail to Conexant Reader Response@conexant.com. Sorry, we can't answer your technical questions at this address. Please contact your local Conexant sales office (listed on back page) or applications engineer if you have technical questions.
D860DSA
Conexant
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
2.0
Inputs and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 2.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.3 2.3.1 2.3.2 2.3.3 2.4 2.4.1 Initialization and Power-up Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 The P Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 The VID Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 The OSD Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Overlay Modes and Alpha Blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Alpha Pin Blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Content-based Blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 ITU-R BT.601 Configurations and Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 ITU-R BT.656 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 VID Port (Video Decoder Locked) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Crystal Inputs and the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Digital Video Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Configurations and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
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Table of Contents
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0
Digital Processing and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 Video Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Analog Horizontal Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Analog and Digital Vertical Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Analog Video Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Subcarrier and Burst Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Subcarrier Phasing (SC_H Phase). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Noninterlaced Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Chrominance Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Internal Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Internal Colorbars, Blue Field, and Black Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 YUV and RGB Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Programming Values to Comply with YPrPb and RGB . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Programmable Video Adjustments Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.2.7.1 Hue Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.2.7.2 Brightness Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.2.7.3 Contrast Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.2.7.4 Saturation Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.2.7.5 Sharpness Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 Macrovision Encoding (Bt861 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Luminance Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Special SCART Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Output Connection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Output Filtering and SINX/X Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 Low Power Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 Teletext Operation of Bt860/861 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.2.15.1 Teletext Timing Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.2.15.2 Teletext Timing Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.2.15.3 General Teletext Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 Wide Screen Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 Copy Generation Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 Closed Captioning and Extended Data Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.2.18.1 Closed Captioning Pass-through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.2.8 3.2.9 3.2.10 3.2.11 3.2.12 3.2.13 3.2.14 3.2.15
3.2.16 3.2.17 3.2.18
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Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table of Contents
4.0
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 PC Board Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Power and Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Device Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 COMP Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 VREF Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 VBIAS Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 ESD and Latchup Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
5.0
Serial Programming Interface and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.4 5.2.1 Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Writing Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Reading Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Register Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Register Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
6.0
Parametric Data and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1 6.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
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Table of Contents
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
vi
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
List of Figures
List of Figures
Figure 1-1. Figure 1-2. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 3-17. Figure 3-18. Figure 3-19. Figure 3-20. Figure 4-1. Figure 4-2. Figure 5-1. Figure 5-2. Figure 5-3. Figure 6-1. Figure 6-2. Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Pixel Latching and Blending Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Alpha Blending Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Timing Mode 1 Connection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Timing Mode 2 Connection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Pixel Timing for Timing Modes 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Timing Mode 3 and 4 Connection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 625 Line ITU-R BT.656 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 525 Line ITU-R BT.656 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Video Decoder Connection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Timing and Clock Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 NTSC Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 PAL Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Luminance Upsampling Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Luminance Upsampling Filter with Peaking and Reduction Options . . . . . . . . . . . . . . . . . 3-13 Close-Up of Luminance Upsampling Filter with Peaking and Reduction Options . . . . . . . 3-14 Luminance Reduction Filters Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Luminance Peaking Filter Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Chrominance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Chrominance Wide Bandwidth Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 SECAM High Frequency Pre-emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 SECAM Low Frequency Pre-emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 YUV Video Format (Internal Colorbars) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 RGB Video Format (Internal Colorbars). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Composite and S-Video Format (Internal Colorbars). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 SCART Function on ALTADDR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Teletext Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 P:Q Ratio Counter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 WSS Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 CGMS Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 Closed Captioning or Extended Data Service Waveform (Null Sequence) . . . . . . . . . . . . . 3-30 Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Recommended Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Serial Programming Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Serial Programming Interface Typical Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Serial Programming Interface Typical Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Pixel and Control Data Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 80 MQFP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
D860DSA
Conexant
vii
List of Figures
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
viii
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
List of Tables
List of Tables
Table 1-1. Table 2-1. Table 2-2. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 4-1. Table 5-1. Table 5-2. Table 5-3. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Alpha Blending Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Configurable Timing States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Target Video Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Register Programming Values for NTSC and PAL Video Standards (ITU-R BT.601) . . . . . . . 3-4 Register Programming Values for NTSC and PAL Video Standards (Square Pixel) . . . . . . . . 3-6 Register Programming Values for SECAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 100/0/75/0 Colorbars as Described in EIA-770.1. EIA-770.1. . . . . . . . . . . . . . . . . . . . . . . . 3-16 100/0/75/0 Colorbars for a 625-Line System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Composite and Luminance Amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Composite and Chrominance Magnitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 DAC Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 P:Q Ratio Counter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 Teletext Line Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 Closed Captioning and Extended Data Services Control Bits . . . . . . . . . . . . . . . . . . . . . . . . 3-29 Typical Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Serial Address Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Video Quality Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
D860DSA
Conexant
ix
List of Tables
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
x
Conexant
D860DSA
1
1.0 Functional Description
1.1 Pin Descriptions
Figure 1-1. Pinout Diagram
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VID1 VID0 VDD GND SIC SID TTXDAT TTXREQ VIDFIELD CLKIN CLKO VPLL XTO XTI PG ND GND VDD RESET* ALTADDR GND
VID2 VID3 VID4 VID5 VID6 VID7 VDD G ND VIDCLK VIDVALID VIDVACT VIDHACT P0 P1 P2 P3 G ND VDDMAX P4 P5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80-pin MQFP
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AGND DACA DACB DACC VBIAS1 VAA COMP1 FSADJ1 VAA AGND AGND VREF FJADJ2 COMP2 VAA VBIAS2 DACD DACE DACF AGND
P6 P7 BLANK* VSYNC* HSYNC* FIELD GND VDD ALPHA0 ALPHA1 OSD0 OSD1 OSD2 OSD3 OSD4 OSD5 GND VDD OSD6 OSD7
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
861_027
D860DSA
Conexant
1-1
1.0 Functional Description
1.1 Pin Descriptions
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 1-1. Pin Assignments (1 of 3)
Pin Name I/O Pin # PRIMARY VIDEO PORT
P[7:0] I 22-19, 16-13 Primary video input port (TTL compatible)(1). Accepts pixel data in 8-bit YCrCb 4:2:2 format in either ITU-R BT.601 or ITU-R BT.656 control formats. A higher index corresponds to a greater bit significance. By default, data is latched on the rising edge of the system clock(2). 2x pixel clock output. The clock generated by the PLL is produced at this pin when register bit CLKO_DIS = 0. Vertical sync input/output (TTL compatible). As an output (master mode operation), VSYNC* follows the rising edge of the system clock. As an input (slave mode operation), VSYNC* is, by default, registered on the rising edge of the system clock(2). The VSYNCI register bit controls the polarity of this signal. Horizontal sync input/output (TTL compatible). As an output (master mode operation), HSYNC* follows the rising edge of the system clock. As an input (slave mode operation), HSYNC* is, by default, registered on the rising edge of the system clock(2). The HSYNCI register bit controls the polarity of this signal. Composite blanking control input (TTL compatible). By default, BLANK* is registered on the rising edge of the system clock(2). The video data inputs are ignored while BLANK* is a logical 0. The BLANKI register bit controls the polarity of this signal. Field control output (TTL compatible). FIELD transitions after the rising edge of the system clock, two clock cycles following a falling HSYNC*. The FIELDI register bit controls the polarity of this signal. The state of this pin at power-up determines the default state of the PCLK_SEL register bit and the initial clock source. If not externally loaded, this pin will be pulled low with an internal pull-down resistor.
Description
CLKO VSYNC*
O I/O
70 24
HSYNC*
I/O
25
BLANK*
I
23
FIELD
O
26
SECONDARY VIDEO PORT
VID[7:0] I 6-1, 80-79 Secondary video input port (TTL compatible). Accepts pixel data in 8-bit YCrCb 4:2:2 format. A higher index corresponds to a greater bit significance. By default, data on the VID port is latched by the rising edge of VIDCLK(1) (3). Pixel clock for secondary video input port(1). Horizontal active display region. A logical 1 indicates data on VID[7:0] is in the horizontal display region. The VIDHACTI register bit controls the polarity of this signal. By default, data on VIDHACT is latched by the rising edge of VIDCLK(1) (3). Vertical active display region. The VIDVACTI register bit controls the polarity of this signal. By default, data on VIDVACT is latched by the rising edge of VIDCLK(1) (3). Field indicator for video input port. A logical 1 indicates data is from an even field. The VIDFIELDI register bit controls the polarity of this signal. By default, data on VIDFIELD is latched by the rising edge of VIDCLK(1) (3). Video data valid qualifier. A logical 1 indicates data on VID[7:0] is valid data. The VIDVALIDI register bit controls the polarity of this signal. By default, data on VIDVALID is latched by the rising edge of VIDCLK(1) (3).
VIDCLK VIDHACT
I I
9 12
VIDVACT VIDFIELD
I I
11 72
VIDVALID
I
10
1-2
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 1-1. Pin Assignments (2 of 3)
Pin Name I/O Pin # Description GRAPHIC AND BLENDING PINS
OSD[7:0] ALPHA[1:0] I I 40-39, 36-31 30-29
1.0 Functional Description
1.1 Pin Descriptions
Dedicated graphic overlay port (TTL compatible.) Accepts pixel data in 8-bit YCrCb 4:2:2 format. Data is latched on the rising edge of the system clock(1) (2). Alpha blend pins. Provides for 1-, 2-, or 4-bit external blend selection between video and graphic overlay data. Data is latched on the rising edge of the system clock(1) (2).
TELETEXT AND SERIAL CONTROL INTERFACE
TTXDAT TTXREQ ALTADDR I O I/O 74 73 62 Teletext data input (TTL compatible)(1). Teletext request output (TTL compatible). Alternate slave address input (TTL compatible). This pin is sampled immediately following a power-up or pin reset. A logical 1 corresponds to write address of 0x88 and a read address of 0x89, while a logical 0 corresponds to a write address of 0x8A and a read address of 0x8B. See Chapter 5.0, for more detail. This pin also provides special SCART signals when register field SCART_SEL00. Serial programming interface data input/output (TTL compatible). Data is written to and read from the device via this serial bus. Serial programming interface clock input (TTL compatible). The maximum clock rate is 400 kHz.
SID SIC
I/O I
75 76
ANALOG VIDEO
DACA DACB DACC DACD DACE DACF FSADJ1 FSADJ2 O O O O O O I 59 58 57 44 43 42 53 48 DAC A output. See Table 3-9. DAC B output. See Table 3-9. DAC C output. See Table 3-9. DAC D output. See Table 3-9. DAC E output. See Table 3-9. DAC F output. See Table 3-9. Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these pins and AGND control the full-scale output current of the DACs. For standard operation, use the nominal values shown under Recommended Operating Conditions. FSADJ1 controls DACs A/B/C and FSADJ2 controls DACs D/E/F. Voltage reference pin. A 1.0 F ceramic capacitor must be used to decouple this pin to AGND. The capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. Compensation pin. A 0.1 F ceramic capacitor must be used to decouple this pin to VAA. The capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. DAC bias voltage. Use a 0.1 F ceramic capacitor to bypass this pin to AGND; the capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum.
VREF
O
49
COMP1 COMP2 VBIAS1 VBIAS2
O
54 47 56 45
O
D860DSA
Conexant
1-3
1.0 Functional Description
1.1 Pin Descriptions
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 1-1. Pin Assignments (3 of 3)
Pin Name I/O Pin # SYSTEM PINS
CLKIN RESET* I I 71 63 2x pixel clock input (TTL compatible). Reset control input (TTL compatible). Setting to zero resets video timing (horizontal, vertical, subcarrier counters to the start of VSYNC of first field), the serial control interface, and all registers. RESET* must be a logical 1 for normal operation. Holding this pin low for 50 clocks or more will ensure that all functions are properly reset. Crystal input for PLL. Crystal output for PLL.
Description
XTI XTO
I O
67 68
POWER AND GROUND
VAA VDD AGND GND VPLL PGND VDDMAX
NOTE(S):
(1) (2)
-- -- -- -- -- -- I
55, 46, 52 7, 28, 38, 64, 78 41, 50, 51, 60 8, 17, 27, 37, 61, 65, 77 69 66 18
Analog power. See Section 4.1 of this document. Digital power. See Section 4.1 of this document. Analog ground. See Section 4.1 of this document. Digital ground. See Section 4.1 of this document. Dedicated power supply for PLL. Dedicated ground for PLL. This pin must be tied to the maximum digital input value. Use 3.3 V if only 3.3 V inputs are used, and 5 V if 3.3/5 V inputs are used.
If these inputs are not used, they should be connected to GND. These input are normally sampled on the rising edge of the system clock, but can be sampled on the falling edge by setting register bit PCLK_EDGE = 1. (3) These inputs are normally sampled on the rising edge of VIDCLK, but can be sampled on the falling edge by setting register bit VIDCLK_EDGE = 1.
1-4
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
1.0 Functional Description
1.2 Functional Overview
1.2 Functional Overview
The Bt860/861 is a highly programmable 3.3 V multiport digital video encoder with pixel synchronization and per-pixel blending capabilities. It is equipped with three 8-bit YCrCb data ports that allow a variety of video and graphic overlay configurations useful in video set top box applications. The three 8-bit YCrCb data ports allow two video streams and one alpha-blended overlay stream. For switching between video sources (such as a video decoder and an MPEG source), while providing a common OSD interface using the part's overlay and alpha capabilities. The Bt860/861's VID port uses a PLL and FIFO to allow direct interfacing with asynchronous video sources, such as the Bt835 video decoder. In slave mode, the Bt860/861 can be configured to accept either ITU-R BT.656-compliant timing (EAV and SAV codes) or ITU-R BT.601 data timing (HSYNC* and VSYNC* signals). The Bt860/861 can also act as timing master, producing ITU-R BT.601 timing. The Bt860/861 supports worldwide video standards, including: * NTSC-M (N. America, Taiwan, Japan) * PAL-B, D, G, H, I (Europe, Asia) * PAL-M (Brazil) * PAL-N (Uruguay, Paraguay) * PAL-Nc (Argentina) * PAL-60, NTSC-443 * SECAM The Bt860/861 has six 10-bit current-out video DACs, specifically designed for video systems requiring the generation of high quality composite, Y/C (S-Video), and simultaneous component YUV or RGB (SCART) video signals. Two of the composite output signals can be programmed with a 0-7 clock luminance delay. The connection status of each DAC can be dynamically monitored through the serial programming interface. The Bt860/861 has several low power options, including sleep mode (only the serial programming interface and PLL are operational), individual DAC disable, PLL disable, and 3.3 V operation. The 3.3 V digital inputs can be configured to be 5 V-tolerant. The luminance upsampling filter is enhanced to provide a narrow transition region and a low stopband. Programmable luminance sharpness filters provide 0,1, 2, and 3.5 dB peaking options at higher video frequencies, and four reduction filters are added for smoothed step response. To reduce the complexity of the required reconstruction filter, 2x upsampling is implemented. The Bt860/861 can produce internally generated colorbars and blue field signals. A 400 kHz serial programming interface (I2C-compatible) is provided for fast system programming. The Bt860/861 provides support for Closed Captioning (CC) and Extended Data Services (XDS), Teletext (WST system B), Copy Generation Management System (CGMS), VARIS-II, and Wide Screen Signaling (WSS). The Bt860 and Bt861 are functionally identical except that the Bt861 can output the Macrovision 7.x anticopy algorithm.
D860DSA
Conexant
1-5
1-6
VREF FSADJ2 FSADJ1 VBIAS1 VBIAS2 Y
FB
1.2 Functional Overview
ALPHA[1:0] SID CRCB
FB
2 Alpha Mixing SIC ALTADDR
Internal Voltage Reference
10
OSD[7:0]
8 Serial Control Interface
1.0 Functional Description
P[7:0]
8
COMP1
Figure 1-2. Detailed Block Diagram
656 Decoder 8 10 SYNC_AMP
COMP2
Video Timing Control M_Y TTXDAT TTXREQ
Sync Processor Y
HSYNC* VSYNC* BLANK* FIELD X
Luma Delay
10 10
DAC DAC
DAC A
8 PLL and Clock Generation M_CR M_CB Luminance 2x Upsample and Cross Color Peaking Filt.
Color Space Convert
+
Closed Captioning, Macrovision
Teletext and CGMS
DAC B 10
DAC
Conexant
+
X 9
Modulator, 10 Mixer and SECAM Filt.
FIFO and Locking Control
CVBS
DAC C
Out U/V Mux
VID[7:0] VIDCLK VIDVALID VIDHACT VIDVACT VIDFIELD
RGB CVBS DLY
X X
10 10
DAC DAC
DAC D DAC E
CLKIN
+
CLKO XTI XTO
Burst Processor
C
X
10
DAC
DAC F
1.3 MHz LPF and 2X Upsample/ Matrix Multiplication
M_COMP_F
HUE_OFF
M_COMP_E M_COMP_D
Multiport YCrCb to NTSC/PAL /SECAM
BST_AMP
Bt860/861
861_028
D860DSA
2
2.0 Inputs and Timing
2.1 Reset
The Bt860/Bt861 has the following reset methods: * * * power-up reset RESET* pin reset software reset register bit
Power-up reset occurs when the part is powered-up. A pin reset occurs when the RESET* pin is held low. (It is recommended that the pin be held low for a minimum of 50 system clock cycles.) Both power-up and pin reset cause the initialization of all chip functions, including video timing and serial programming registers. Writing a 1 to register bit SRESET (1B[7]) resets all serial programing registers to their default states, listed in Section 5.0.
2.1.1 Initialization and Power-up Configuration
At power-up all registers reset to their initial values (see Section 5.0). The state of the FIELD pin at power-up (or pin reset) determines the default state of the PCLK_SEL register bit and the initial clock source. If the FIELD pin is pulled high, the initial clock source is the CLKIN pin; if the FIELD pin is pulled low, the initial clock source is from the PLL and requires a crystal at the XTI and XTO pins. If not loaded, the FIELD pin is pulled low with the pin's internal pull-down resistor. The power-up configuration is interlaced NTSC-M, 27 MHz black burst video, as listed in the default values of the register bit map.
NOTE:
To enable active video, black burst video must be turned off by setting register bit EACTIVE (1D[1]) to 1. Other video configurations must be programmed using the part's serial programming interface registers.
D860DSA
Conexant
2-1
2.0 Inputs and Timing
2.2 Digital Video Ports
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
2.2 Digital Video Ports
Internally, data to the Bt860/861 is treated as either video, overlay, or alpha data. Video data is the primary visual program content, while overlay data is used for informational or navigational content displayed over the visual program. Alpha data controls the pixel blending of the video and overlay content. Sufficient flexibility exists in the Bt860/861 to allow for a variety of source and blending configurations and interesting visual effects. Video data is supplied by either the P (Primary Video) port, or the VID (Secondary Video) port. Overlay data can be supplied by either the P port or the OSD (On Screen Display) port. Alpha data can be supplied by the ALPHA port, or embedded in the two LSBs of the overlay luminance data. Figure 2-1 illustrates the pixel latching and blending mechanism.
Figure 2-1. Pixel Latching and Blending Mechanism
ALPHA
2
2
Blend Detection 4 2
OSD
8
8 Overlay Stream
P
8
OVERLAY_SEL
Pixel Blender
8
VID VIDCLK VIDVALID VIDHACT VIDVACT VIDFIELD CLKIN XTI XTO CLKO
8 VIDEO_SEL
8 Video Stream
PLL and Clock Logic
861_042
2-2
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
2.0 Inputs and Timing
2.2 Digital Video Ports
2.2.1 The P Port
The P port can accept video data from a variety of digital video sources. It is designed specifically to interface directly with commercial MPEG video decoders and D1 digital video sources. The P port supports both ITU-R BT.601 timing (HSYNC* and VSYNC* signals), and ITU-R BT.656 timing (SAV and EAV codes). Data on the P[7:0] pins can be treated as either video or overlay data, controlled by the VIDEO_SEL (1A[3]) and OVRLAY_SEL (1A[4]) register bits (see Figure 2-1). Data on this port must be presented in 8-bit YCrCb 4:2:2 digital video format. The P[7:0] pins are latched using the system clock as configured using register bits PCLK_SEL (19[7]) and PCLK_EDGE (19[1]).
2.2.2 The VID Port
The VID port is specially configured for broadcast video sources, such as from a television tuner or local cable system. It can accept a 27 MHz YCrCb 4:2:2 video stream at the same pixel rate as the other ports, or it can accommodate alternate clock rates, such as the 8xFsc clock rate used by the Bt835 family of video decoders. Since the time base for these sources is external to the system and therefore asynchronous to the local pixel clock, the Bt860/861 provides a mechanism that synchronizes these two domains. When using the VID port in locking mode, the Bt860/861 immediately synchronizes its vertical timing to the vertical timing presented on the VIDVACT pin, and gradually adjusts its horizontal timing and clock rate to further synchronize with the VID port. VIDCLK latches the incoming data into a FIFO, and data is extracted at the appropriate pixel rate for internal processing. The average active horizontal pixel count must be equal to the value programmed into the HACTIVE register field. For example, the Bt835 generates pixels at a rate of 14.32 Mpix/s when used for NTSC video capture, but the actual valid pixel count per line is determined by the video mode required. For support of 27 MHz streams, 720 valid pixels will be delivered per line. This configuration is compatible with other video devices connected to the Bt860/861 and running with a continuous pixel rate of 13.5 Mpix/s. The Bt860/861 will generate the necessary video timing and pixel clock to act as master for the other video device. The VID port can be configured as the video source by setting register bit VIDEO_SEL (1A[3]) to 1. Data on this port must be presented in 8-bit YCrCb 4:2:2 digital video format.
2.2.3 The OSD Port
The OSD port is functionally very similar to the P port, except that it cannot decode ITU-R BT.656 timing. As the overlay source, this port can be mixed with the video stream using one of the alpha-mixing modes described in Section 2.2.5. While intended as an overlay source, the OSD port can be configured to be the sole image content by using the appropriate blend programming. The overlay source is selected by setting register bit OVRLAY_SEL (1A[4]) to 1. Data on this port must be presented in 8-bit YCrCb 4:2:2 digital video format. The OSD[7:0] pins are latched using the system clock as configured by register bits PCLK_SEL (19[7]) and PCLK_EDGE (19[1]).
D860DSA
Conexant
2-3
2.0 Inputs and Timing
2.2 Digital Video Ports
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
2.2.4 Overlay Modes and Alpha Blending
The Bt860/861 can be configured to display only a single video stream, or to mix any combination of two data ports (P, VID, and OSD). Programming register field ALPHAMODE (1A[6:5]) to 00 and register bit BLENDMODE (1A[7]) to 1 selects the internal video bus as the sole source of data, regardless of the alpha source. In this mode, either the VID port or the P port can be used as the video source, which is selected by register bit VIDEO_SEL (1A[3]). Other combinations of the ALPHAMODE and BLENDMODE programming will allow blending of the video and overlay buses. Table 2-1 lists all valid input modes.
Table 2-1. Alpha Blending Configurations
Configuration
Blending depth Overlay source Alpha Source Video source ALPHAMODE BLENDMODE
Programming
Use ALPHA_LUT_X No Yes Yes No Yes Yes Yes No Yes No Yes Yes No Yes OVERLAY_SEL X 0 0 0 0 1 1 1 1 X 1 1 1 1 VIDEO_SEL 1 1 1 1 1 1 1 1 1 0 0 0 0 0
VID VID VID VID VID VID VID VID VID P P P P P
None P P P P OSD OSD OSD OSD None OSD OSD OSD OSD
None ALPHA[1:0] ALPHA[1:0] ALPHA[1:0] P LSBs ALPHA[1:0] ALPHA[1:0] ALPHA[1:0] OSD LSBs None ALPHA[1:0] ALPHA[1:0] ALPHA[1:0] OSD LSBs
None 1 bit 2 bit 4 bit 2 bit 1 bit 2 bit 4 bit 2 bit None 1 bit 2 bit 4 bit 2 bit
1 1 1 1 0 1 1 1 0 1 1 1 1 0
00 01 10 11 XX 01 10 11 XX 00 01 10 11 XX
NOTE(S): X or XX = Don't care.
Data from the overlay source may be applied with varying levels of transparency, from fully transparent, no overlay, to fully opaque, full overlay. A 4-bit blend multiplier provides sixteen levels of mixing. The value 1111 is a special case allowing the overlay data to pass completely unmixed. In all other cases the value applied to the video path is (1 - blend / 16), and the value applied to the overlay path is (blend / 16), where blend is the 4-bit multiplier value. Two methods are used to generate the 4-bit multiplier. The multiplier value can come either from a four-entry by 4-bit lookup table (LUT), or directly from the ALPHA pins. In both cases, the blend multiplier value will be applied to both luma and chroma for the co-sited components (Cb0:Y0:Cr0) and a separate multiplier applied for the (Y1) component.
2-4
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
2.0 Inputs and Timing
2.2 Digital Video Ports
2.2.5 Alpha Pin Blending
The ALPHA[1:0] pins are used to select the amount of blending per pixel when BLENDMODE = 1. The pins are sampled at the system clock rate and samples during both luma and chroma components may be captured to create 1-, 2-, or 4-bit blend factors. For 1- and 2-bit blend modes, the multiplier LUT (in registers ALPHA_LUT_0 through ALPHA_LUT_3 is programmed with user-defined multiplier values. In 1-bit blend mode, the ALPHA[0] pin indexes registers ALPHA_LUT_0 and ALPHA_LUT_3 to generate the multiplier value. In 2-bit blend mode, the ALPHA[1:0] pins are used as a 2-bit index for registers ALPHA_LUT_0 through ALPHA_LUT_3. In 4-bit blend mode, the four bits required are captured in successive load clocks from ALPHA[1:0]. The two LSBs of the 4-bit value are latched during the luma portion of the overlay data load, and the two MSBs are latched during the chroma component load. These four bits provide a direct multiplier for the blending module. Figure 2-2 illustrates the alpha blending timing diagram.
Figure 2-2. Alpha Blending Timing Diagram
System Clock 8-bit Overlay OSD[7:0]/P[7:0] Data ALPHA[1] ALPHA[0] ALPHA[1] ALPHA[0] ALPHA[1] ALPHA[0] OSD[1]/P[1] OSD[0]/P[0]
A[0]0 A[0]1 A[0]2 A[0]3 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3
4-bit Alpha
A[3]0 A[2]0
A[1]0 A[0]0
A[3]1 A[2]1
A[1]1 A[0]1
A[3]2 A[2]2
A[1]2 A[0]2
A[3]3 A[2]3
A[1]3 A[0]3
2-bit Alpha
A[1]0 A[0]0
A[1]1 A[0]1
A[1]2 A[0]2
A[1]3 A[0]3
1-bit Alpha
2-bit Contentbased Alpha
A[1]0 A[0]0
A[1]1 A[0]1
A[1]2 A[0]2
A[1]3 A[0]3
NOTE(S):
1. Shaded areas indicate which video components are affected by each multiplier or index. 2. A blank data packet means this data carries no alpha information.
861_026
2.2.6 Content-based Blending
Content-based blending uses the two LSBs of the overlay byte associated with the luma pixel to address the multiplier lookup table (registers ALPHA_LUT_0 through ALPHA_LUT_3). This method is selected by setting BLENDMODE = 0, and is a convenient means of using blending when no alpha pins exist from the overlay device.
D860DSA
Conexant
2-5
2.0 Inputs and Timing
2.3 Configurations and Timing
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
2.3 Configurations and Timing
The Bt860/861 is capable of various ITU-R BT.601, ITU-R BT.656, and decoder-locked configurations. Table 2-2 lists several ITU-R BT.601 and ITU-R BT.656 configurations, and Section 2.3.3 discusses decoder-locked configurations. In any of these configurations, it is possible to synchronize a primary video source with an alternate video source. These two sources can then be alpha-mixed, or independently selected for external display. Alpha mixing is discussed in detail in Section 2.2.5.
Table 2-2. Configurable Timing States
Description
Bt860/861 is timing master, HSYNC*, VSYNC*, and FIELD(1), are outputs. Bt860/861 is timing slave, timing derived from HSYNC*, VSYNC*, and BLANK* signals(2). Bt860/861 is timing slave, timing derived from ITU-R BT.656 codes. HSYNC*, and VSYNC* are unused. Bt860/861 is timing slave, timing derived from ITU-R BT.656 codes. HSYNC*, VSYNC*, and FIELD(1) are outputs.
NOTE(S):
(1)
Timing Mode
SLAVE
EN_656
SYNC_CFG
1
0
0
1
2
1
0
X
3
1
1
0
4
1
1
1
Decoder locking using the VID port requires the part to be in timing mode 1, except SYNC_CFG = 1 is only required if synchronization with other sources is required. (2) Either the BLANK* pin or the HBLANK, VBLANK, HACTIVE, and VACTIVE register can be used for blanking. 3. Configurations not listed are not recommended. 4. X = Don't care.
2-6
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
2.0 Inputs and Timing
2.3 Configurations and Timing
2.3.1 ITU-R BT.601 Configurations and Timing
Master and slave ITU-R BT.601 configurations are listed in Table 2-2 as timing modes 1 and 2. Timing mode 1 is the ITU-R BT.601 master mode. An example connection diagram is illustrated in Figure 2-3. In this example, both video sources are slaved to the Bt860/861. .
Figure 2-3. Timing Mode 1 Connection Example
Video Slave 8
Bt860/861
P[7:0] HSYNC* VSYNC* CLKO(1) FIELD
Optional OSD Source, Timing Slave
8 2
OSD[7:0] ALPHA[1:0] XTI XTO
NOTE(S):
(1)
It is not required that the clock be sourced from the Bt860/861.
861_009
D860DSA
Conexant
2-7
2.0 Inputs and Timing
2.3 Configurations and Timing
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Timing mode 2 is the ITU-R BT.601 slave mode. An example connection diagram is illustrated in Figure 2-4. In this example, the source feeding the P port is the timing master, and both the optional OSD source and the Bt860/861 are timing slaves. Although additional sources are shown in these diagrams, it is not necessary to have more than one video source.
Figure 2-4. Timing Mode 2 Connection Example
Video Master 8 Bt860/861
P[7:0] HSYNC* VSYNC* CLKIN(1) BLANK*
Optional OSD Source, Timing Slave
8 2
OSD[7:0] ALPHA[1:0]
NOTE(S):
(1)
It is not required that the clock is sourced external to the Bt860/861.
861_007
When the Bt860/861 is configured for ITU-R BT.601 timing, the HSYNC*, VSYNC*, FIELD, and BLANK* pins synchronize the Bt860/861 to external video sources. In master mode, HSYNC* field, and VSYNC* are outputs and the BLANK* pin is not used. All timing is generated internally and blanking is determined by the HBLANK, VBLANK, HACTIVE, and VACTIVE registers. In slave mode, HSYNC*, VSYNC* and BLANK* are inputs and the encoder's timing is controlled by an external master. Blanking is set either by the internal HBLANK, VBLANK, HACTIVE, and VACTIVE registers (register bit BLK_IGNORE = 1) or by a blanking signal on the BLANK* pin (register bit BLK_IGNORE = 0).
2-8
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
2.0 Inputs and Timing
2.3 Configurations and Timing
If the registers are used to determine video blanking (register bit BLK_IGNORE = 1), the first component of the first active pixel of a line should be presented to the encoder at HBLANK + 2 rising system clock edges after the falling edge of HSYNC* for master mode, and HBLANK + 3 rising system clock edges after the falling edge of HSYNC* for slave mode. The correct order of the pixel components is Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2.... Figure 2-5 illustrates this timing relationship.
Figure 2-5. Pixel Timing for Timing Modes 1 and 2
t1(1)
Video Out
t3(3)
t2(2)
Pixel Data Pixel Timing System Clock
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
t4(4)
HSYNC* BLANK*
t5(5)
NOTE(S):
(1)
(2) (3) (4) (5)
Blanking times (t1) are listed in Tables 3-1 through 3-4. Desired front porch blanking is set by the HBLANK register. HBLANK = t1 + 14 The number of active pixels per line (t2) is set by the HACTIVE register. The total number of system clocks per line (t3) is set by the HCLK register. The first component of the first active pixel of the line should be placed HBLANK + 2 (or 3 for slave mode) rising system clock edges after falling HSYNC*(t4) in order to coincide with the end of horizontal blanking. When the BLANK* pin is used, the first component of the first pixel must arrive 3 rising system clock edges after the falling edge of BLANK* (t5 ).
861_006
If the BLANK* signal is used to determine video blanking (in slave mode only), the first component of the first active pixel of a line should be presented to the encoder three rising system clock edges after the falling edge of the BLANK* signal. Figure 2-5 illustrates this relationship.
D860DSA
Conexant
2-9
2.0 Inputs and Timing
2.3 Configurations and Timing
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
The HBLANK register sets the line blanking time from the midpoint of the falling edge of the analog horizontal sync pulse to the end of blanking. The HACTIVE register sets the number of active pixels after the horizontal blanking period has ended. See Tables 3-1 through 3-4 for appropriate HBLANK and HACTIVE programming values for various NTSC, PAL, and SECAM video standards. Pixel and data timing (P, OSD, ALPHA, HSYNC*, VSYNC*, BLANK*) are by default, latched into the Bt860/861 on the rising edge of the system clock, but can be latched on the falling edge of the system clock if register bit PCLK_EDGE (19[1]) is set high. The system clock can be seen on CLKO or CLKIN when appropriate. Legal setup and hold times must be observed.
2.3.2 ITU-R BT.656 Timing
Data on the P port can be routed through the part's ITU-R BT.656 timing translator only when the system clock is 27 MHz, by setting register bit EN_656 (1A[2]) high. This is accomplished using timing modes 3 or 4 (see Table 2-2). Figure 2-6 illustrates an example connection diagram. ITU-R BT.656 timing derives vertical and horizontal timing information from the video data stream (SAV and EAV codes). These codes are internally converted to HSYNC* and VSYNC* signals, which can be then be produced on the Bt860/861's HSYNC*, VSYNC*, and FIELD pins. ITU-R BT.656 timing (also known as D1 timing) is illustrated in Figures 2-7 and 2-8. The resultant video is automatically aligned to conform to ITU-R BT.656 video and blanking placement. The contents of the HBLANK, HACTIVE, VACTIVE, and VBLANK registers are ignored, except when register bit BLK_IGNORE = 1.
Figure 2-6. Timing Mode 3 and 4 Connection Example
CCIR656 Timing, Video Master 8 P[7:0] CLKIN(1) Bt860/861
OSD Source, Timing Slave 8 OSD[7:0] HSYNC* VSYNC* FIELD
2
ALPHA[1:0]
NOTE(S):
(1)
It is not required that the clock is sourced external to the Bt860/861.
861_010
2-10
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
2.0 Inputs and Timing
2.3 Configurations and Timing
Figure 2-7. 625 Line ITU-R BT.656 Timing
OH Analog Line n - 1 Analog Line n
Digital Line n - 1 Digital Blanking Luminance Samples 717 Cr Samples 359 Cb Samples 359 360 365 366 360 365 366 718 719 720 721 12 T 730 731 732 733 132 T
Digital Line n
862
863
0
1
2
431
0
1
431
0
1
T : luminance sampling period
861_005a
Figure 2-8. 525 Line ITU-R BT.656 Timing
OH Analog Line n - 1 Analog Line n
Digital Line n - 1 Digital Blanking Luminance Samples 717 Cr Samples 359 Cb Samples 359 360 367 368 360 367 368 718 719 720 721 16 T 734 735 736 737 122 T
Digital Line n
856
857
0
1
2
428
0
1
428
0
1
T : luminance sampling period
861_005b
D860DSA
Conexant
2-11
2.0 Inputs and Timing
2.3 Configurations and Timing
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
In this configuration, the Bt860/861 is a slave to the ITU-R BT.656 data stream. However, the HSYNC*, VSYNC* and FIELD pins can be configured as outputs for synchronization with a video slave on the OSD port. While in this configuration, the HSYNC*, VSYNC*, and FIELD timing is identical to ITU-R BT.601 master mode timing.
2.3.3 VID Port (Video Decoder Locked) Timing
The VID port can accept video signals from a video decoder, such as the Bt835, and is buffered using a FIFO to support asynchronous video streams. The internal logic will automatically pulls data from the FIFO when required. The data lines for the VID port are VID[7:0], and the control lines are VIDCLK, VIDHACT, VIDVACT, VIDFIELD, and VIDVALID. Figure 2-9 illustrates an example configuration using the Bt835 and the Bt860. The PLL and the horizontal and vertical counters are adjusted to track the incoming data on the VID port. The Bt860/861 can be configured to output HSYNC* and VSYNC* signals in order to synchronize with the P, OSD, and ALPHA signals. Timing mode 1 must be used when the VID port is selected in conjunction with a source on the P or OSD ports. The PLL (using the XTI and XTO inputs) must be selected as the system clock source.
2-12
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Figure 2-9. Video Decoder Connection Example
Bt835 Video Decoder 8 Bt860/861
2.0 Inputs and Timing
2.3 Configurations and Timing
VD[15:8] CLKX2 VALID ACTIVE VACTIVE FIELD
VID[7:0] VIDCLK VIDVALID VIDHACT VIDVACT VIDFIELD
MPEG-2 Decoder 8
P[7:0] CLKO HSYNC* VSYNC* FIELD
Graphic Processor 8 OSD[7:0]
2
ALPHA[1:0] XTI XTO
861_008
Follow these steps to lock a video decoder to this port: 1. Connect to the data and control pins as illustrated in Figure 2-9. 2. Select the correct effective clock frequency using the PLL_FRACT and PLL_INT registers, and choose the XTAL inputs as the system clock source using register bit PCLK_SEL (19[7]). See Section 2.4.1, and the PLL_FRACT and PLL_INT register descriptions. 3. Set these locking registers to the following values: FIELD NAME XL_MDSEL[1:0] XL_SATEN XL_SAT[3:0]
4. 5.
VALUE 11 1 1
Set the part for Timing Mode 1 (see Table 2-2). Initiate locking by setting the LOCK (1C[5]) register bit high and the LC_RST (1C[6]) register bit low. When unlocking the Bt861 to a source on the VID port, set the LOCK (1C[5]) register bit low and the LC_RST (1C[6]) register bit high.
NOTE:
D860DSA
Conexant
2-13
2.0 Inputs and Timing
2.4 Clock Selection
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
2.4 Clock Selection
The internal pixel clock (PCLK) can be derived from either the CLKIN input or the crystal inputs. The PCLK_SEL register bit (19[7]) controls which of these two inputs will become the pixel clock.
2.4.1 Crystal Inputs and the PLL
The crystal inputs (XTI and XTO) drive a buffered oscillator to create a clock. This clock is routed through the PLL if register bit BY_PLL (1D[3]) is 0, and bypasses the PLL untouched if BY_PLL is 1. Figure 2-10 illustrates the clock block diagram. If PCLK_SEL is low, this becomes the system clock. The PLL_FRACT and the PLL_INT registers determine the PLL clock frequency multiplier. The default setting generates a 27.0 MHz clock, using a 14.31818 MHz crystal. If the VID port is enabled using the LOCK (1C[5]) register bit, the PLL is controlled by the tracking servo mechanism. The frequency programmed through PLL_FRACT and PLL_INT is used as a base around which the VID port locking mechanism adjusts the system clock. The PLL_FRACT and PLL_INT registers remain unaffected by the locking mechanism, and when locking is disabled (through the LOCK bit), the PLL_FRACT and PLL_INT registers once again determine the exact PLL frequency.
Figure 2-10. Timing and Clock Block Diagram
OSD[7:0]
8 8
OSD[7:0] P[7:0] VID[7:0]
3 1 0 EN_656 SLAVE PCLK_SEL 1 0 Xtal Inverter and Buffer 1 PLL 0 BY_PLL CLKO_DIS System Clock 3 Encoder Timing Block System Block
P[7:0]
8
CCIR656 Timing Translator 3
HSYNC* VSYNC* BLANK* CLKIN
XTI XTO CLKO VIDCLK VID[7:0]
8
FIFO
8
861_025
2-14
Conexant
D860DSA
3
3.0 Digital Processing and Functionality
3.1 Video
3.1.1 Video Standards
The Bt860/861 supports worldwide video standards, including NTSC-M (N. America, Taiwan, Japan), PAL-B, D, G, H, I (Europe, Asia), PAL-M (Brazil), PAL-N (Uruguay, Paraguay), PAL-Nc (Argentina), PAL-60, NTSC-443, and SECAM. Table 3-1 lists the target video timing and amplitude used to generate the appropriate register programming for various forms of NTSC, PAL, and SECAM as listed in Tables 3-2, 3-3, and 3-4 respectively. These tables provide the programming values of only those registers required to create that particular video standard. Ancillary data, input configuration, and ignored or common value register values are not shown. Video parameter registers which are not relevant to a particular standard are described as such in the register detail section of this document. Table 3-2 lists the register values required to program the various forms of PAL and NTSC in ITU-R BT.601 resolution, and Table 3-3 lists the register values required to program the various forms of PAL and NTSC in square pixel resolution. Table 3-4 lists register values required to program the encoder for SECAM output, with and without synchronization bottleneck pulses.
D860DSA
Conexant
3-1
3
3-2
Video Standard NTSC-M 4.7 0.286 150 200 5.6 2.25 (10 cycles) 4433618.75 0.3 YES 625 15625 50 NO 22(3) 262(3) 9.2 9.2 NO 23(4) 309(4) 10.5 [9.778] YES 625 15625 50 YES 23(4) 309(4) 9.2 5.3 2.514 (9 cycles) 3579545 0.2857 NO 525 15734.264 59.94 YES 22(3) 262(3) 9.2 [9.037] 9.2 9.2 262(3) 262(3) 22(3) 22(3) 22(3) 262(3) NO YES YES 59.94 59.94 59.94 15734.264 15734.264 15734.264 525 525 525 525 15734.264 59.94 NO NO YES YES 0.2857 0.2857 0.306 0.3 0.3 3579545 4433618.75 3579611.49 4433618.75 4433618.75 2.514 (9 cycles) 2.25 (10 cycles) 2.52 (9 cycles) 2.25 (10 cycles) 2.25 (10 cycles) 5.3 5.3 5.8 5.3 5.6 150 150 150 150 200(1) 0.286 0.2857 0.2857 0.3 0.3 0.2857 0.3 200 5.6 2.51 (9 cycles) 3582056.25 0.3 YES 625 15625 50 NO 23(4) 309(4) 10.5 4.7 4.7 4.7 4.7 4.7 4.7 4.7 NTSC-J NTSC-443 PAL-M PAL-60 PALB,D,G,H,I PAL-N PAL-Nc 4.7 0.3 200 5.6 N/A for=4406250, fob=4250000 0.161 NO 625 15625 50 NO 23(4) 309(4) 10.5 SECAM
Table 3-1. Target Video Parameters (1 of 2)
Parameter Description
HSYNC Width (s)
HSYNC and VSYNC Height (V)
HSYNC Rise/Fall Time (10% to 90%) (ns)
Burst or Subcarrier Start (s)
Burst Width (s)
Subcarrier Frequency(2) (Hz)
Burst or Subcarrier Height (V)
Conexant
Phase Alternation
Number of Lines per Frame
Line Frequency (Hz)
Field Frequency (Hz)
Setup
First Active Line
Last Active Line
Multiport YCrCb to NTSC/PAL /SECAM
HSYNC to Blank End (s)(5)
Bt860/861
D860DSA
Table 3-1. Target Video Parameters (2 of 2)
Video Standard NTSC-M 1.5[1.185] 0.661 3 3 3 3 3 2.5 3 2.5 0.714 0.661 0.661 0.7 0.7 0.661 0.7 1.5 1.5 1.5 1.5 1.5[0.889] 1.5 1.5 NTSC-J NTSC-443 PAL-M PAL-60 PALB,D,G,H,I PAL-N PAL-Nc 1.5 0.7 2.5 SECAM
Multiport YCrCb to NTSC/PAL /SECAM
D860DSA
Bt860/861
Parameter Description
Blank Begin to HSYNC (s)(5)
Black to 100% White (V)
Number of Lines each for Vertical Serration, Equalization
NOTE(S):
(1)
(2)
Value for PAL-I is 250 ns. When programming the subcarrier increment, use relationship of Fsc to Fh as given in ITU-R BT.470 instead of Fsc and Fclk. (3) Using NTSC line numbering convention from ITU-R BT.470. (4) Using PAL line numbering convention from ITU-R BT.470. (5) ITU-R BT.601 blanking values given in square brackets []
Conexant
3-3
3
3-4 Video Standard Register No.
16[5] 0 0 0 0 0 1 1
Table 3-2. Register Programming Values for NTSC and PAL Video Standards (ITU-R BT.601) (1 of 2)
Parameter Description NTSC-M NTSC-J PAL-M NTSC-443 PAL-60 PAL-N
Register Name
PALB,D,G,H,I
PAL-Nc
1
Number of Lines
625LINE
Width of Analog Horizontal Sync Pulse 08[7:0] 7F 7E 7F 7F 7F 7F 1F[7:0] 1D[0] 16[2] 0 0 0 0 0 1 1 1 1 1 7A 7B 5E 7A 5E 5D 1 0
AHSYNC_WIDTH
7F
7F
Burst Amplitude
BURST_AMP
5D 1 0
5D 1 0
Cross Color Filter Off
CROSSFILT
Frequency Modulated 07[1:0]/06[7:0] 2C9 2C9 2C9 2C9
FM
Conexant
0C[1:0]/0B[7:0] 108 108 108 108 09[7:0] 0A[7:0] 05[3:0]/04[7:0] 21[7:0] 20[7:0] 22[7:0] C7 9A 8D 6B4 6B4 9B DA A5 54 52 8C 8E 9A 5C 6B4 8D C7 9A 8C 54 6B4 8D C7 9A
Number of Active Pixels Per Line
HACTIVE
2C9
2BF
2CF
2BF
Number of System Clocks from OH to HBLANK Active Video
108
128
108
128
Beginning of Burst HBURST_BEG
8F 52 6B4 9B DA 9A
95 51 6C0 9B DA A2
95 51 6C0 9B DA A2
95 58 6C0 9B DA A2
End of Burst
HBURST_END
Number of System HCLOCK Clocks Per Line
Cb Multiplier
M_CB
Cr Multiplier
M_CR
Multiport YCrCb to NTSC/PAL /SECAM
Bt860/861
D860DSA
Y Multiplier
M_Y
Table 3-2. Register Programming Values for NTSC and PAL Video Standards (ITU-R BT.601) (2 of 2)
Video Standard Register No.
29[7:0]/28[7:0] 27[7:0]/26[7:0] 21F07C1F 0 0 00 0 1 E4 0F1 13 13 13 0F1 0F1 0F1 13 E4 E4 E4 0 1 1 0 F0 0F1 13 0 0 1 1 00 00 00 00 00 0 0 F0 11F 17 0 1 0 1 1 0 0 0 0 0 0 1 00 0 1 E4 11F 17 21F07C1F 21F0A527 2A098ACB 2A098ACB 2A098ACB 16[1] 16[3] 38[7:0] 16[7] 16[4] 1E[7:0] 0F[0]/0E[7:0] 0D[7:0] 2A098ACB
Multiport YCrCb to NTSC/PAL /SECAM
D860DSA NTSC-M NTSCJAPAN PAL-M NTSC-443 PAL-60 PAL-N PALB,D,G,H,I PAL-Nc
21F69446 0 1 00 0 0 F0 11F 17 16[6] 0 0 0 0 0 1 0 1
Bt860/861
Parameter Description
Register Name
Subcarrier Increment
MSC_DR
Interlace Off
NI
Phase Alternation
PAL
Subcarrier Phase Offset
PHASE_OFF
Subcarrier Reset
SC_RESET
SETUP
SETUP
Conexant
Sync Tip to Blank Amplitude
SYNC_AMP
Number of Active Lines
VACTIVE
Number of Blanked VBLANK Lines from OV
Analog and Digital Vertical Sync VSYNC_DUR Duration
NOTE(S): Internal timing and the values programmed into the registers reference the analog VSYNC pulse (OV) as line #1 (see Figures 3-1 and 3-2).
3-5
3-6 Video Standard NTSC-M System Clock Frequency (MHz) Register No.
16[5] 0 0 0 0 0 1
Table 3-3. Register Programming Values for NTSC and PAL Video Standards (Square Pixel) (1 of 2)
NTSCJAPAN PAL-M NTSC-443 PAL-60 PAL-N
PALB,D,G,H,I
PAL-Nc
Parameter Description 24.5454 24.5454 24.5454 24.5454 24.5454 29.5
Register Name
29.5
1
29.5
1
Number of Lines
625LINE
Width of Analog Horizontal Sync Pulse 08[7:0] 74 74 74 74 74 1F[7:0] 1D[0] 16[2] 0 0 0 0 1 1 1 1 7C 7C 5F 7A 5D 1 0
AHSYNC_WIDTH
8A
8A
8A
Burst Amplitude
BURST_AMP
5D 1 0
5D 1 0
5D 1 0
Conexant
07[1:0]/06[7:0] 289 289 289 289 0C[1:0]/0B[7:0] 0F0 0F0 0F0 0F0 09[7:0] 0A[7:0] 05[3:0]/04[7:0] 618 3D 80 80 3D 618 8B 4A 618 80 3D 618
Cross Color Filter Off
CROSSFILT
Frequency Modulated
FM
Number of Active Pixels Per Line
HACTIVE
289
300
314
300
Number of System Clocks from OH to HBLANK Active Video
0F0
140
11C
140
Beginning of Burst HBURST_BEG
80 3D 618
A4 65 760
A4 65 760
A4 6E 760
End of Burst
HBURST_END
Multiport YCrCb to NTSC/PAL /SECAM
Number of System HCLOCK Clocks Per Line
Bt860/861
D860DSA
Table 3-3. Register Programming Values for NTSC and PAL Video Standards (Square Pixel) (2 of 2)
Video Standard Register No.
21[7:0] 20[7:0] 22[7:0] 29[7:0]/28[7:0]/ 27[7:0]/26[7:0] 25555555 0 0 00 0 1 E4 0F1 13 13 0F1 0F1 13 E4 E4 0 1 1 E4 0F1 13 0 0 1 00 00 00 0 1 0 1 00 1 0 F0 0F1 13 0 0 0 0 25555555 254BF631 2E3DB902 2E3DB902 16[1] 16[3] 38[7:0] 16[7] 16[4] 1E[7:0] 0F[0]/0E[7:0] 0D[7:0] 26798C0C 0 1 00 0 0 F0 11F 17 99 A6 99 99 A2 A2 CB DC CB CB D8 D8 D8 A2 26798C0C 0 1 00 0 1 E4 11F 17 90 9C 90 90 99 99 99
Multiport YCrCb to NTSC/PAL /SECAM
D860DSA NTSC-M NTSCJAPAN PAL-M NTSC-443 PAL-60 PAL-N PALB,D,G,H,I PAL-Nc
99 D8 A2 1F15C01E 0 1 00 0 0 F0 11F 17 16[6] 0 0 0 0 0 1 0 1
Bt860/861
Parameter Description
Register Name
Cb Multiplier
M_CB
Cr Multiplier
M_CR
Y Multiplier
M_Y
Subcarrier Increment
MSC_DR
Interlace Off
NI
Phase Alternation
PAL
Subcarrier Phase Offset
PHASE_OFF
Conexant
Subcarrier Reset
SC_RESET
SETUP
SETUP
Sync Tip to Blank Amplitude
SYNC_AMP
Number of Active Lines
VACTIVE
Number of Blanked VBLANK Lines from OV
Analog and Digital Vertical Sync VSYNC_DUR Duration
NOTE(S): Internal timing and the values programmed into the registers reference the analog VSYNC pulse (OV) as line #1 (see Figures 3-1 and 3-2).
3-7
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3
Table 3-4. Register Programming Values for SECAM
System Clock Frequency (MHz) 27
Number of Lines Width of Analog Horizontal Sync Pulse Cross Color Filtering Off Upper Db Limit Lower Db Limit Upper Dr Limit Lower Dr Limit Bottleneck Pulses FM Modulation Number of Active Pixels per Line Number of System Clocks from OH to Active Video Beginning of Subcarrier Number of System Clocks Per Line Cb Multiplier Cr Multiplier Y Multiplier Subcarrier Increment for Db Subcarrier Increment for Dr Interlace Off Phase Alternation Programmable Subcarrier Mode Subcarrier Amplitude Subcarrier Phase Pattern Setup Sync Tip to Blank Amplitude Number of Active Lines Number of Blanked Lines from OV(2) Analog and Digital Vertical Sync Duration
NOTE(S):
(1) (2)
Parameter Description
Register Name
Register Number
29.5
1 8B 0 529 43B 529 43B 0(1) 1 300 140 A5 760 9A BB A4 24E1A08B 263CBEEA 0 0 0 85 0 0 F0 11F 17 1
625 Line AHSYNC_WIDTH CR0SSFILT DB_MAX DB_MIN DR_MAX DR_MIN FIELD_ID FM HACTIVE HBLANK HBURST_BEG HCLOCK M_CB M_CR M_Y MSC_DB MSC_DR NI PAL PROG_SC SC_AMP SC_PATTERN SETUP SYNC_AMP VACTIVE VBLANK VSYNC_DUR
16[5] 08[7:0] ID[0] 34[1:0]/33[7:0] 36[1:0]/35[7:0] 30[1:0]/2F[7:0] 32[1:0]/31[7:0] 1B[6] 16[2] 07[1:0]/06[7:0] 0C[1:0]/0B[7:0] 09[7:0] 05[3:0]/04[7:0] A2 C5 22[7:0] 2D[7:0]/2C[7:0] 2B[7:0]/2A[7:0] 29[7:0]/28[7:0] 27[7:0]/26[7:0] 16[1] 16[3] 1A[1] 86 1A[0] 16[4] 1E[7:0] 0F[0]/0E[7:0] 0D[7:0] 16[6]
1 7F 0 5A3 49F 5A3 49F 0(1) 1 2C0 128 97 6C0 94 B5 A4 284BDA13 29C71C72 0 0 0 86 0 0 F0 11F 17 1
To enable synchronization bottleneck pulses, this bit must be 1. Internal timing and the values programmed into the registers reference the analog VSYNC pulse (OV) as line #1 (see Figures 3-1 and 3-2).
3-8
Conexant
D860DSA
3.1 Video
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.1 Video
3 3.0 Digital Processing and Functionality
3.1.2 Analog Horizontal Sync
The duration of the horizontal sync pulse is determined by register HSYNC_WIDTH (12[7:0]). The beginning of the horizontal sync pulse corresponds to the reset of the internal horizontal pixel counter. The sync rise and fall times are automatically controlled. The horizontal and vertical sync amplitude is programmable using register SYNC_AMP (IE[7:0]).
3.1.1
3.1.3 Analog and Digital Vertical Sync
The duration of the analog and digital vertical sync is determined by register bit VSYNC_DUR (16[6]). If VSYNC_DUR = 0, 3.0 lines are selected; if VSYNC_DUR = 1, 2.5 lines are selected. Tables 3-2, 3-3, and 3-4 list the appropriate VSYNC_DUR settings for all supported standards. Figures 3-1 and 3-2 illustrate 3.0 and 2.5 lines respectively.
Figure 3-1. NTSC Vertical Timing
OV(1) Odd Field
Even Field
NOTE(S):
(1)
Internal timing considers this point the start of the field (vertical reset).
861_032
D860DSA
Conexant
3-9
3.0 Digital Processing and Functionality
3.1 Video
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Figure 3-2. PAL Vertical Timing
OV(1) Odd Field
Even Field
NOTE(S):
(1)
Internal timing considers this point the start of the field (vertical reset).
861_033
3.1.4 Analog Video Blanking
In master mode, and when register bit BLK_IGNORE = 1 in slave mode, register fields HBLANK, VBLANK, HACTIVE, and VACTIVE control analog video blanking. Together they define the active region, where pixels will be displayed. VBLANK defines the number of lines from the leading edge of the analog vertical sync (Ov) to the first active line (see Figures 3-1 and 3-2). VACTIVE defines the number of active lines. HBLANK defines the number of system clocks (minus 14) from the leading edge of horizontal sync to the first active pixel. HACTIVE defines the number of active pixels per line. In the slave mode, when BLK_IGNORE = 0, the BLANK* pin determines analog blanking. The video from the start of horizontal sync through the end of the burst, as well as the vertical lines with serration and equalization pulses is automatically blanked.
3-10
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.1 Video
3.1.5 Subcarrier and Burst Generation
The Bt860/861 uses a 32-bit subcarrier increment to synthesize the subcarrier. The value of the subcarrier increment required to generate the desired subcarrier frequency for NTSC and PAL formats is found by: M_SC_DR[31:0] = int (232 x fsc / fclk + 0.5) where fclk is the encoder system clock rate and fsc is the desired subcarrier frequency. When available, use the relationship between HCLK and the subcarrier frequency as given in ITU-R BT.470. For example: NTSC-M: M_SC_DR[31:0] = int {[455 / (2 x HCLK)] x 232 + 0.5} PAL-B: M_SC_DR[31:0] = int {[(1135 / 4 + 1 / 625) / HCLK] x 232 + 0.5} Tables 3-2 and 3-3 lists the programming values for common NTSC and PAL standards. For SECAM formats, the two subcarrier frequency increments are defined by: SECAM Dr: M_SC_DR[31:0] = int [(fsc / fclk) x 232 + 0.5] SECAM Db: M_SC_DB[31:0] = int [(fsc / fclk) x 232 + 0.5] Table 3-4 lists standard programming values for SECAM. The HBURST_BEG register determines the start of burst (or subcarrier for SECAM). In PAL and NTSC video formats the HBURST_END register determines the end of the burst. The BURST_AMP register controls burst amplitude. The burst is automatically blanked during the horizontal sync to prevent generation of invalid sync pulses. Burst blanking is automatically controlled and depends on which video format is selected. Burst rise and fall times are internally controlled. The SC_AMP register controls the SECAM subcarrier amplitude. In addition, generation of the "bottleneck signals" for subcarrier line synchronization may be enabled using the FIELD_ID register bit. Registers PROG_SC and SC_PATTERN allow control of active line placement and subcarrier phase sequencing.
D860DSA
Conexant
3-11
3.0 Digital Processing and Functionality
3.1 Video
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.1.6 Subcarrier Phasing (SC_H Phase)
For PAL and NTSC video formats, the subcarrier phase is set to 0 on the leading edge of the analog vertical sync every four (NTSC) or eight (PAL) fields, unless the SC_RESET bit is set to a logical 1. This is true for both interlaced and non-interlaced outputs. In addition, the subcarrier phase can be adjusted by the PHASE_OFF register. Each LSB change of PHASE_OFF corresponds to a 360 / 256 degree change in the phase. Setting SC_RESET to 1 is useful when the subcarrier phase at the end of a color field sequence is significantly different from 0.
3.1.7 Noninterlaced Operation
When programmed for noninterlaced master mode, the Bt860/861 always displays the odd field. The FIELD signal stays low to indicate that the field is always odd. A 30 Hz offset should be subtracted from the color subcarrier frequency while in NTSC mode so the color subcarrier phase will be inverted from field to field. Transition from interlaced to noninterlaced in master mode occurs during odd fields to prevent synchronization disturbance.
NOTE:
Consumer VCRs can record noninterlaced video with minor noise artifacts, but special effects (e.g., scan >2x) may not function properly.
3-12
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.2 Effects
3.2 Effects
3.2.1 Chrominance Disable
Setting register bit DCHROMA (17[2]) to 1 turns off the chrominance subcarrier and colorburst.
3.2.2 Internal Filtering
Once the input data is converted to internal YUV format, the Y and UV components are filtered and upsampled to the system clock frequency. The luminance signal is always low-pass filtered using the upsampling filter response illustrated in Figure 3-3. Additional peaking or reduction filters can be enabled (see Figures 3-4 and 3-5), using the PKFIL_SEL register field and the FIL_SEL register bit. When register bit FIL_SEL is set to 0, register field PKFIL_SEL selects the peaking filters illustrated in Figure 3-7. When register bit FIL_SEL is set to 1, register field PKFIL_SEL selects the reduction filters illustrated in Figure 3-6. The peaking filters are optimized for high bandwidth frequency response, and the reduction filters are optimized for step response performance. The default chrominance filter response is illustrated in Figure 3-8, but an alternate wide bandwidth response can be selected using register bit CHROMA_BW, as illustrated in Figure 3-9. SECAM pre-emphasis filter responses are illustrated in Figures 3-10 and 3-11.
.
Figure 3-3. Luminance Upsampling Filter
Figure 3-4. Luminance Upsampling Filter with Peaking and Reduction Options
0
0 -10
-10 -20 Amplitude in dB
Amplitude in dB
0 2 4 6 8 Frequency in MHz 10 12
861_015
-30 -40 -50 -60 -70 -80
-20
-30
-40
-50 -60
0
2
4
6 8 Frequency in MHz
10
12
861_016
D860DSA
Conexant
3-13
3.0 Digital Processing and Functionality
3.2 Effects
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Figure 3-5. Close-Up of Luminance Upsampling Filter with Peaking and Reduction Options
Figure 3-6. Luminance Reduction Filters Options
2
0
0
Amplitude in dB
Amplitude in dB 0 1 2 3 4 5 Frequency in MHz 6 7 8
861_017
-5
-2
-4
-10
-6
-15 -8
-20
-10
0
1
2
3 4 Frequency in MHz
5
6
861_018
Figure 3-7. Luminance Peaking Filter Options
4 3.5
Figure 3-8. Chrominance Filter
0
-10 3 Amplitude in dB 2.5 2 1.5 1 0.5 0 Amplitude in dB 0 1 2 3 4 Frequency in MHz 5 6
861_019
-20
-30
-40
-50
-60 0 0.5 1 1.5 2 2.5 Frequency in MHz 3 3.5 4
861_022
Figure 3-9. Chrominance Wide Bandwidth Filter
0
Figure 3-10. SECAM High Frequency Pre-emphasis Filter
16 14
-10 12 Amplitude in dB Amplitude in dB -20 10 8 6 4 -50 2 0 0 1 2 3 4 Frequency in MHz 5 6
861_023a
-30
-40
-60
3.5
4 4.5 Frequency in MHz
5
861_021
3-14
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.2 Effects
Figure 3-11. SECAM Low Frequency Pre-emphasis Filter
10
8 Amplitude in dB
6
4
2
0
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7 Frequency in MHz
0.8
0.9
1
861_023
3.2.3 Internal Colorbars, Blue Field, and Black Burst
The Bt860/861 can be configured to generate 100% amplitude, 75% saturation (100/7.5/75/7.5 for NTSC/PAL-M with set-up, 100/0/75/0 for PAL/SECAM) colorbars by setting register bit ECBAR (17[1]) bit to a 1. The Bt860/861 can also produce a blue field by setting register bit BLUE_FLD (17[6]) to 1, and black burst by setting register bit EACTIVE (1D[1]) to 0. Pixel inputs are ignored while any of these waveforms are being produced. Example colorbars for different output formats are illustrated in Figures 3-12, 3-13, and 3-14. Specific levels are listed in Tables 3-5 through 3-8.
D860DSA
Conexant
3-15
3.0 Digital Processing and Functionality
3.2 Effects
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Figure 3-12. YUV Video Format (Internal Colorbars)
Magenta
Yellow
Green
White
Awht Async Ayel Acyn
Amgt Agrn
Ared Ablu Ablk
y
Acyn Awht
Amgt Agrn Ared Ablu Ablk
V(Pb)
Ayel
Amgt Awht Ayel Agrn Ablu Ablk
Ared
U(Pr)
Acyn
NOTE(S): All "Ax" values are relative to black, except for Ablk and Async, which are relative to blank.
861_012
Table 3-5. 100/0/75/0 Colorbars as Described in EIA-770.1. EIA-770.1
Async(1)
Y (volts) Pr (volts) Pb (volts)
NOTE(S):
(1)
Black
Cyan
Blue
Red
Awht
0.714 0 0
Ayel
0.465 0.043 -0.262
Acyn
0.368 -0.262 0.089
Agrn
0.309 -0.220 -0.174
Amgt
0.217 0.220 0.174
Ared
0.157 0.262 -0.089
Ablu
0.060 -0.043 0.262
Ablk(1)
0 0 0
-0.286 0 0
EIA-770.1 states that setup can be either "none or 7.5" IRE. If setup = 0, then Awht = 714 V, but if setup = 7.5 IRE, then Awht = 0.661 V. 2. All "Ax" values are relative to black, except Ablk, and Async which are relative to blank.
3-16
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.2 Effects
Figure 3-13. RGB Video Format (Internal Colorbars)
Magenta
Yellow
Green
White
Awht
Ayel
Acyn
Agrn
Amgt
Ared
Ablu
Ablk
R
Awht
Ayel
Acyn
Agrn
Amgt
Ared
Ablu
Ablk
G
Awht
Ayel
Acyn
Agrn
Amgt
Ared
Ablu
Ablk
B
NOTE(S): All "Ax" values are relative to black, except for Ablk and Async, which are relative to blank.
861_013
Table 3-6. 100/0/75/0 Colorbars for a 625-Line System
Async(1)
R (volts) G (volts) B (volts)
NOTE(S):
(1)
Awht
0.700 0.700 0.700
Ayel
0.525 0.525 0
Acyn
0 0.525 0.525
Agrn
0 0.525 0
Amgt
0.525 0 0.525
Ared
0.525 0 0
Ablu
0 0 0.525
Black
Cyan
Blue
Red
Ablk
0 0 0
0 0 0
The Bt860/861 supports RGB that employes an external sync signal. For external sync, use the composite or S-Video luminance waveform. 2. Complies with SMPTE 253. 3. All "Ax" values are relative to black, except Ablk, and Async which are relative to blank.
D860DSA
Conexant
3-17
3.0 Digital Processing and Functionality
3.2 Effects
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Figure 3-14. Composite and S-Video Format (Internal Colorbars)
Magenta
Yellow
Green
White
Myel Mcyn
Awht Mb Async Ayel Acyn
Mgrn Mmgt Mred
Agrn
Amgt
Mblu
Ablk
Composite
Ared Ablu
Awht Ayel Async Acyn Agrn Amgt Ared Ablu Ablk
y
S Video
Mb Mwht Mblk Myel Mcyn Mgrn Mmgt Mred Mblu Blank Level
C
NOTE(S):
1. Ax is the DC (luminance) amplitude referenced to black, except for Ablk and Async, which are referenced to blank. 2. Mx numbers are the peak-to-peak amplitudes of the subcarrier waveform.
861_011
Table 3-7. Composite and Luminance Amplitude
Y and Composite Amplitudes
NTSC-M (volts) NTSC-J (volts) PAL-B (volts)
NOTE(S):
Async
-0.286 -0.286 -0.300
Awht
0.661 0.714 0.700
Ayel
0.441 0.477 0.465
Acyn
0.347 0.375 0.368
Agrn
0.292 0.316 0.308
Amgt
0.203 0.220 0.217
Ared
0.149 0.161 0.157
Black
Cyan
Blue
Red
Ablu
0.054 0.059 0.060
Ablk
0.0536 0 0
Ax is the DC (luminance) amplitude referenced to black, except for Ablk and Async, which are referenced to blank.
3-18
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.2 Effects
Table 3-8. Composite and Chrominance Magnitude
C and Composite Magnitudes
NTSC-M (volts) NTSC-J (volts) PAL-B (volts)
Mb
0.286 0.286 0.300
Mwht
0 0 0
Myel
0.444 0.480 0.470
Mcyn
0.630 0.681 0.663
Mgrn
0.589 0.636 0.620
Mmgt
0.589 0.636 0.620
Mred
0.629 0.681 0.664
Mblu
0.444 0.480 0.470
Mblk
0 0 0
Mx numbers are the peak-to-peak amplitudes of the subcarrier waveform.
3.2.4 Setup
Setting the SETUP register bit to 1 places a 0.054 V (7.5 IRE) pedestal between blank and black. SETUP only affects Composite, Y of S-Video, Y of YUV, and RGB waveforms.
3.2.5 YUV and RGB Multipliers
When the output format of DACs D, E, and F is YUV or RGB, registers M_COMP_D (23[7:0]), M_COMP_E (25[7:0]) and M_COMP_F (24[7:0]) are amplitude multipliers. The gain range is from 0x to 2x, where a register value of 0x80 gives a gain of 1.
3.2.6 Programming Values to Comply with YPrPb and RGB
To comply with EIA 770.1 on 525-line systems for YPrPb values (listed in Table 3-5), start with the programming values listed in Table 3-2, then use these multipliers: Value (NTSC-J) 0x80 0x90 0x66 Value (NTSC-M) 0x80 0x90 0x66
Register 0x23 0x24 0x25
To attain the RGB values shown in Table 3-6, start with the programming values listed in Table 3-2, then use these multipliers: Value (PAL-B, D, G, H, I) 0x80 0x80 0x80
Register 0x23 0x24 0x25
D860DSA
Conexant
3-19
3.0 Digital Processing and Functionality
3.2 Effects
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.2.7 Programmable Video Adjustments Controls
Registers Y_OFF, M_Y, M_CB, M_CR, and PHASE_OFF program video adjustment controls for hue, brightness, contrast, saturation, and sharpness. 3.2.7.1 Hue Adjust There are two methods for adjusting the hue. Only one method should be enabled at any time. While using one method, the registers of the other should be set to their default values. Method 1--adjusts the subcarrier phase within the active video region. Register HUE_ADJUST (3B[7:0]) controls the subcarrier phase. This method adjusts the hue in composite and S-Video signals for PAL and NTSC waveforms according to the following equation:
HUE_ADJUST = 256 x ( phase offset ) 360
Method 2--uses the four registers MULT_UU, MULT_VU, MULT_UV, and MULT_VV to matrix multiply the color vectors. These registers are used to perform a 2x2 matrix multiplication on the U/V path (or DR/DB path for SECAM). Matrix multiplication transforms the incoming U/V stream into an outgoing U/V stream preceeding the color modulator. The default values leave the U/V stream unmodified. The parameters are 8-bit twos complement numbers. The formulas implemented by these registers are as follows: Uout = (MULT_UU/128) x Uin + (MULT_VU/128) x Vin Vout = (MULT_UV/128) x Uin + (MULT_VV/128) x Vin The value 0x7F is a special case which is rounded up internally to +128, or a factor of 1.00 after the multiplier is divided by 128. These registers can be loaded with sine and cosine values as follows to perform a hue rotation on the chrominance values, except a value of +127 is made 128 internally. To rotate the hue by an angle , program the matrix multipliers as follows: MULT_UU = 128 x cos () MULT_VU = -128 x sin () MULT_UV = 128 x sin () MULT_VV = 128 x cos () Method 2 (matrix multiplication) cannot be used for hue rotation when the PAL bit is enabled. However, hue rotation can be accomplished for PAL modes in one of two ways. For component modes, method 2 hue rotation (matrix multiplication) is effective if register bit PAL (16[3]) is set to 0. For composite and S-Video modes, in which register bit PAL is enabled, method 1 hue rotation (subcarrier phase adjust) is effective. Hue rotation cannot be implemented simultaneously for component and composite PAL modes. When in SECAM mode, this matrix multiplication occurs in D R/DB space, and, as a result, the angle should be the negative of what one would expect if the data was in the U/V space for PAL or NTSC. 3.2.7.2 Brightness Adjust Brightness adjust is controlled by register Y_OFF (37[7:0]). Y_OFF is a twos compliment number, such that a value of 0x00 is 0 IRE offset, a value of 0x7F is +22.14 IRE offset, and a value of 0x80 is -22.31 IRE offset. The luminance level offset is referenced from black and can be adjusted from -22.31 IRE (below black) to +22.14 IRE (above black). Active video is added to the offset level.
3-20
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.2 Effects
3.2.7.3 Contrast Adjust 3.2.7.4 Saturation Adjust
Register M_Y (22[7:0]) controls contrast adjustment. This modifies the luminance multiplier, allowing a larger or smaller luminance range. Registers M_CB (21[7:0]) and M_CR (20[7:0]) control saturation adjustments. These registers are the chrominance component (Cb and Cr) multipliers. To maintain the correct Cb/Cr relationship, these registers should be modified synchronously. Register field PKFIL_SEL (1B[4:3]) and register bit FIL_SEL (3C[2]) control sharpness filters. When FIL_SEL = 0, peaking filters of 0 dB, 1 dB, 2 dB and 3.5 dB gains are selected by register field PKFIL_SEL. When FIL_SEL = 1, four reduction filters are selected by register field PKFIL_SEL. Figures 3-6 and 3-7 illustrates these filter options.
3.2.7.5 Sharpness Adjust
D860DSA
Conexant
3-21
3.0 Digital Processing and Functionality
3.2 Effects
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.2.8 Macrovision Encoding (Bt861 Only)
The anticopy process contained within the Bt861 is implemented according to the version 7.x. Specification, developed by Macrovision Corporation in Sunnyvale, California. The Macrovision Anticopy process is available only in the Bt861. Conexant cannot ship Bt861 encoders to any customer until Macrovision has licensed that customer. Contact Macrovision Corporation to obtain this license agreement. Parties who have obtained a Macrovision license may receive the Bt861 Macrovision Supplement by contacting their local Conexant Sales office.
3.2.9 Outputs
Register field OUTMODE (17[5:3]) is used to select one of eight analog output configurations, as listed in Table 3-9. All DACs are designed to drive standard video levels into a combined Rload of 37.5 (double-terminated 75 ) To minimize supply current, disable unused outputs by setting the corresponding DIS_DAC_x register bit high.
Table 3-9. DAC Format Options
Bits
000 001 010 011 100 101 110 111
DAC A
Y Y Y Y CVBS CVBS CVBS Y
DAC B
C C C C CVBS_DLY CVBS_DLY CVBS_DLY C
DAC C
CVBS CVBS CVBS Y CVBS CVBS CVBS CVBS
DAC D
Y R CVBS_DLY Y Y R CVBS_DLY CVBS_DLY
DAC E
V G CVBS C V G CVBS C
DAC F
U B CVBS C U B CVBS Y
NOTE(S): CVBS_DLY is the composite video signal with an optional luminance component
delayed as controlled by the YDELAY register field.
3.2.10 Luminance Delay
Register field YDELAY can be programmed with up to 7 clocks delay on any DAC with a CVBS_DLY label (see Table 3-9). The programable luminance delay can be used to correct the high frequency chrominance delay caused by postfiltering.
3-22
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.2 Effects
3.2.11 Special SCART Signals
At power-up, the ALTADDR pin is sampled to determine the Bt860/861's serial programming address. At all other times the SCART_SEL (3C[1:0]) register field determines its function. Setting the SCART_SEL register field to 00 will three-state the ALTADDR pin; setting it to 01 produces a Vertical Blank signal on the ALTADDR pin; setting it to 10 produces a Composite Sync signal on the ALTADDR pin; and setting it to 11 produces a Composite Blank signal on the ALTADDR pin. These signals are 3.3 V TTL signals that are aligned with the outgoing video, as illustrated in Figure 3-15.
Figure 3-15. SCART Function on ALTADDR Pin
Composite Video SCART _SEL [1:0]
ALTADDR Pin (Vertical Blank)
01
ALTADDR Pin (Composite Sync)
10
ALTADDR Pin (Composite Blank)
11
861_034a
3.2.12 Output Connection Status
DAC connection status can be checked automatically or manually. When the AUTO_CHECK (1B[2]) register bit is set to 1, the connection status of the DACs is automatically checked once per frame. When the AUTO_CHECK register bit is set to 0 (default), setting the CHECK_STAT register bit to 1 initiates a single check of the DAC connection status. This bit is automatically cleared. The connection status of the DAC is then represented on the MONSTAT_A through MONSTAT_F register bits (01[7:2]). A 1 indicates that a properly terminated load has been detected on that DAC. Because the Bt860/861 checks for a double terminated load (combined 37.5 ), improper termination causes the load to be misrepresented. The DAC output must be enabled for proper sensing.
D860DSA
Conexant
3-23
3.0 Digital Processing and Functionality
3.2 Effects
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.2.13 Output Filtering and SINX/X Compensation
The DAC output response is a typical sinx/x response. For the composite video output, this results in slightly lower than desired burst and chroma amplitude values. To compensate for this, choose an output filter with high frequency peaking or program the BST_AMP, M_CR, and M_CB registers higher by a factor of (x/sinx). The amplitude of the affected signal is calculated by:
f sc sin ------- f clk Amplitude = ---------------------------f sc ------- f clk
3.2.14 Low Power Features
The Bt860/Bt861 has several power saving features, including 3.3 V operation, individual DAC disable, sleep mode, and PLL disable. The Bt860/861 is a 3.3 V part with 5 V-tolerant digital inputs; 5 V tolerance is obtained by setting the VDDMAX pin to 5 V. If 5 V tolerance is not required, connect VDDMAX to VDD. Setting the SLEEP (1B[0]) register bit to 1 puts the part into sleep mode, in which all blocks are disabled except core serial programming functionality and the PLL. If CLKIN is the internal clock source, power can be further reduced by disabling the PLL and oscillator circuitry by setting the DIS_PLL (1D[4]) and DIS_XTAL (1D[7]) register bit to 1. In sleep mode, only the SLEEP bit is active, so the PLL must be powered down before sleep is induced if disabling the PLL is desired. This mode achieves the greatest reduction in power. All DACs can be disabled individually using the EN_DAC_x (18[5:0]) register bits. This method can be used when not all DACs are required simultaneously.
3-24
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.2 Effects
3.2.15 Teletext Operation of Bt860/861
Teletext encoding in the Bt860/861 is accomplished via a two-wire interface, TTXDAT and TTXREQ, and several control registers, programmed via the serial programming interface. The Bt860/861 Teletext output conforms to Teletext B for 625-line systems; Teletext should be disabled for 525-line systems. For more details on the Teletext standard, consult ITU-R BT.653 or EACEM Technical Report No. 8. The TTXDAT pin is the Teletext data insertion pin, and the TTXREQ pin is the timing pin. The TTXREQ pin can be configured into two Teletext timing modes by using register bit TXRM (59[1]). Figure 3-16 illustrates Teletext timing.
Figure 3-16. Teletext Timing
t1(1)
Composite or Luminance (Y) Output
(2)
Bit 1 2 3 4 5 6 7 8 9 . . . Clock Run-In
TTXDAT
(3)
TTXREQ (Timing Mode 1)
t2(4) Bit 1 2 3 4 5 6 7 8 ...
TTXREQ (Timing Mode 2) t3 (5) t4 (6) HSYNC*
NOTE(S): (unchanged note)
(1) (2) (3) (4) (5) (6)
t1 is the start of Teletext. The midpoint of the first Teletext pulse is 10.2 s from the midpoint of the analog horizontal sync pulse falling edge. The Teletext data on the TTXDAT pin must observe proper set-up and hold times relative to the Teletext timing clock falling edge (TTXREQ signal in timing mode 1). Teletext data is latched on the Teletext timing clock's falling edge. The Teletext timing clock's first rising edge (t2) occurs 335 system clocks after falling HSYNC* for ITU-R BT.601 timing. Placement of the rising edge of the TTXREQ request signal (t3) in Teletext timing mode 2 is definable using register field TXHS[10:0]. Placement of the falling edge of the TTXREQ request signal (t4) in Teletext timing mode 2 is definable using register field TXHE[10:0].
861_001
D860DSA
Conexant
3-25
3.0 Digital Processing and Functionality
3.2 Effects
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.2.15.1 Teletext Timing Mode 1
Setting register bit TXRM to 1 puts the Bt860/861 in Teletext timing mode 1. In this mode, the TTXDAT pin is the Teletext data entry pin, and the TTXREQ pin is configured as the Teletext timing clock. The Teletext clock timing is fixed internally and has an average frequency of 6.9375 MHz. The Teletext timing clock does not have a consistent period, because it is derived from the system clock, which is not evenly divisible by 6.9375 MHz. The clock period varies from 3-4 system clocks for ITU-R BT.601 timing, and 4-5 system clocks for square pixel timing. Teletext data is latched on the falling edge of this clock. The first rising edge occurs 335 system clocks after falling HSYNC* for ITU-R BT.601 timing (27 MHz). Setting register bit TXRM to 0 puts the Bt860/861 in Teletext timing mode 2. In this mode, the TTXDAT pin is the Teletext data entry pin, and the TTXREQ pin is configured as the Teletext data request line. In this mode, the same Teletext timing clock as in mode 1 is fixed internally. The rising edge of the TTXREQ signal means start transmitting data, and the falling edge means stop transmitting data. The 11-bit register fields TTXHS[10:0] and TTXHE[10:0] control the placement of the rising and falling edges. Each LSB represents a one system clock count (27 MHz or 29.5 MHz) increment. When the system clock is 27 MHz, there is a 4 clock offset between the falling edge of HSYNC* and the rising or falling edge of the TTXREQ request signal. For example, a value of 0x001 on either register places the respective edge at 5 clocks from falling HSYNC*. The register values of TTXHS and TTXHE cannot be zero, equal to, or greater than the total number of system clocks per line. The internal Teletext timing clock can be externally reproduced using a P:Q ratio counter, such as the one conceptualized in Figure 3-17. Table 3-10 lists appropriate values for ITU-R BT.601 and square pixel timing.
Figure 3-17. P:Q Ratio Counter Block Diagram
3.2.15.2 Teletext Timing Mode 2
ADDER A P B CO SUM CLK
MODULO Q REGISTER
RSTN ENABLE_TTX_CLK
D CLK
Q
TELETEXT CLOCK
861_004
Table 3-10. P:Q Ratio Counter Values
CLK ITU-R BT.601 Square Pixel
27 MHz 29.5 MHz
Pixel Rate
13.5 MHz 14.75 MHz
P
37 111
Q
144 472
3-26
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.2 Effects
3.2.15.3 General Teletext Operation
A logical 1 on the TTXDAT pin corresponds to an analog output value of 66% of the black-to-white transition (approximately 462 mV above black), and a logical 0 corresponds to black. The Bt860/861 does not automatically provide any Teletext data, such as the clock run-in and framing code; the user must provide all data. Setting register bit TXE to 1 enables Teletext encoding. Register field TTXBF1[8:0] sets the start Teletext line for field 1, and register field TTXEF1[8:0] sets the end Teletext line for field 1. Register field TTXBF2 sets the start Teletext line for field 2, and register field TTXEF2[8:0] sets the end Teletext line for field 2. These 9-bit registers can be set to any value from 0-311, but setting the start line before line 7 is not recommended. The start line should be less than or equal to the end line. If the start and end lines for a field are the same value, Teletext is disabled for that field. Register bit SQUARE must be set to 0 for ITU-R BT.601 timing (27 MHz system clock), and 1 for square pixel timing (29 MHz system clock). The TTX_DIS register field allows the user to disable the Teletext function on specific lines in the odd and even fields as listed in Table 3-11.
Table 3-11. Teletext Line Disable
Register Bit
TTX_DIS[0] TTX_DIS[1] TTX_DIS[2] TTX_DIS[3] TTX_DIS[4] TTX_DIS[5] TTX_DIS[6] TTX_DIS[7]
TTX Line (F1/F2)
8 / 321 9 / 322 10 / 323 11 / 324 12 / 325 13 / 326 14 / 327 15 / 328
Register Bit
TTX_DIS[8] TTX_DIS[9] TTX_DIS[10] TTX_DIS[11] TTX_DIS[12] TTX_DIS[13] TTX_DIS[14] TTX_DIS[15]
TTX Line (F1/F2)
16 / 329 17 / 330 18 / 331 19 / 332 20 / 333 21 / 334 22 / 335 23 / 336
3.2.16 Wide Screen Signaling
Wide Screen Signaling (WSS) is used in 625-line systems on line 23. WSS data is 14 bits long and is entered on register bits WSS[14:1]. Register bits WSSDAT[20:15] are ignored. To enable WSS on field 1, line 23, set register bit EWSSF1 to 1. Register bit EWSSF2 is ignored, because WSS cannot be enabled on field 2. If the clock is at CCIR clock speeds (27 MHz), set register bit SQUARE to 0; if the clock is at square pixel speeds (29.5 MHz), set register bit SQUARE to 1. The clock run-in and start codes are automatically inserted onto the signal, but CRC data is not.
D860DSA
Conexant
3-27
3.0 Digital Processing and Functionality
3.2 Effects
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Figure 3-18 illustrates a typical WSS signal, where WSSDAT[14:1] = 0x00. Note that WSS uses bi-phase coding of its data bits. The amplitude of the WSS pulses is 500 mV above black when high, and black when low. For further WSS details, see specification ETS 300294 or ITU-R BT.1119.
Figure 3-18. WSS Waveform
0.5 V
0.0 V Run-In Start Code Bit 14 14 Data Bits Bit 1
861_002
3.2.17 Copy Generation Management System
Copy Generation Management System (CGMS) is used in 525-line systems on lines 20 and 283 (a.k.a. line 20, field 2). The CGMS data is 20 bits long and is entered on register bits WSSDAT[20:1]. * Set register bit EWSSF1 to 1 to enable CGMS on field 1, line 20. * Set register bit EWSSF2 to 1 to enable CGMS on field 2, line 283. * Set register bit SQUARE to 0 if the clock is at CCIR clock speeds (27 MHz). * Set register bit SQUARE to 1 if the clock is at square pixel speeds (24.5454 MHz). Although there is no clock run-in in CGMS, a reference pulse is provided automatically.
3-28
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
3.0 Digital Processing and Functionality
3.2 Effects
CRC data is not calculated and must be provided by the user. Figure 3-19 illustrates a typical CGMS signal. Note that bit 1 is closest to the HSYNC pulse and bit 20 is farthest. The amplitude of the CGMS pulses are 70 IRE when high, and 0 IRE when low. For further CGMS details, see specifications EIA-J CPR-1202, EIA-J CPR-1204, and IEC 61880.
Figure 3-19. CGMS Waveform
V 1.0 IRE 100
Bit No. 1 2
0.786
70
Reference
3
.. .. ..
20
0.286
0
2.235 s 50 ns
0
-40
11.2 s 0.3 s 49.1 s 0.44 s
Line 20/283
861_003
3.2.18 Closed Captioning and Extended Data Services
The Bt860/861 can produce Closed Captioning (CC) and Extended Data Services (XDS) waveforms for NTSC and PAL on the lines specified by CC_SEL (49[3:0]) and XDS_SEL (49[7:4]), as listed in Table 3-12. Two bytes of CC data are entered using registers CCB1 (42[7:0]) and CCB2(43[7:0]), and two bytes of XDS data are entered using registers XDSB1 (40[7:0]) and XDSB2 (41[7:0]). The data registers are double buffered to prevent accidental overwriting of the data. To enable CC, set register bit ECC (48[0]) high, and to enable XDS, set register bit EXDS (48[1]) high. To prevent writing partial data sequences, data is not latched until the second byte of the two-byte data sequence (CCB2 or XDSB2) is written. Therefore, data must be written in the order Byte 1, then Byte 2.
Table 3-12. Closed Captioning and Extended Data Services Control Bits
0x49 D7 D6 D5 D4 D3 D2 D1 D0
XDS_SEL 525 Line 625 Line 285 336 284 335 283 334 282 333 22 24
CC_SEL 21 23 20 22 19 21
D860DSA
Conexant
3-29
3.0 Digital Processing and Functionality
3.2 Effects
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
The ECCGATE register bit must be 1 for normal operation. When this bit is set to 1, current data is displayed for one frame, and then the NULL data sequence is displayed until new data is written to the registers. If ECCGATE is set to 0, old data is displayed until new data is written to the registers. Register bits CC_STAT (01[0]) and XDS_STAT (01[1]) allow monitoring of data latching and encoding. When CC data is latched into the Bt861 registers, the CC_STAT register bit is set to 1; when the data is encoded, it is set to 0. When XDS data is latched into the Bt861 registers, the XDS_STAT register bit is set to 1; when the data is encoded, it is set to 0. By default, the CC or XDS waveform is placed at an appropriate start point and has a data frequency of 503.4965 kb/s, however, both the start point and signal width can be modified using registers fields CCSTART and CC_ADD, respectively. Figure 3-20 illustrates a typical CC or XDS waveform. The waveform consists of a clock run-in, a start bit, and two bytes of data, which is encoded LSB first. The Bt860/861 automatically creates the clock run-in and start bit, but does not calculate the parity bits. CC and XDS use an NRZ waveform, where a logical 0 is represented by a black, and a logical 1 is represented as 50 IRE. Pixel data is ignored during active CC and XDS lines, but the CC or XDS waveforms will be overwritten by Teletext data when Teletext is active on the CC or XDS line.
Figure 3-20. Closed Captioning or Extended Data Service Waveform (Null Sequence)
MSB Byte 1
MSB Byte 2
50 IRE
Byte 1 Clock Run-in Start Bit 2 Bytes of Data
Byte 2
861_014
3.2.18.1 Closed Captioning Pass-through
There is no explicit means for accepting broadband vertical blanking interval (VBI) content through the data port. However, by expanding the active video region to include the CC line, the device can encode this data properly for output.
3-30
Conexant
D860DSA
4
4.0 Applications
4.1 PC Board Considerations
The layout for the Bt860/861 should be optimized for the lowest noise possible on the power and ground planes by providing good decoupling. The trace length between groups of power and ground pins should be as short as possible to minimize inductive ringing. A well-designed power distribution network is critical for elimination of digital switching noise. The ground plane must provide a low-impedance return path for the digital circuits. A PC board with a minimum of four layers is recommended, with layers 1 (top) and 4 (bottom) for signals, and layers 2 and 3 for ground and power, respectively.
4.1.1 Component Placement
Components should be placed as close as possible to the associated pin so traces can be connected point-to-point. The optimum layout enables the Bt860/861 to be located close to both the power supply connector and video output connectors.
4.1.2 Power and Ground Planes
Separate digital and analog power planes are recommended as illustrated in Figure 4-1. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to the VAA power pins, protection diodes, and COMP decoupling. There should be at least an 1/8-inch gap between the digital and analog power planes, connected by a single point through a ferrite bead. The ground plane should be a single unified plane overlapping both analog and digital power planes. The path back to the power supply should have the lowest impedance possible with only one possible return path. This layout eliminates noise on the analog signals caused by cross-currents from digital switching. The bead separating the digital and analog power planes should be located within three inches of the Bt860/861. The bead provides impedance to switching currents and high frequency noise. Use a low-resistance (<0.5 ) bead, such as Ferroxcube 5659065-3B, Fair-Rite 2723021447, or TDK BF45-4001.
D860DSA
Conexant
4-1
4.0 Applications
4.1 PC Board Considerations
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Figure 4-1. Typical Connection Diagram
5 V(1) VDD VAA C5 COMP 1 COMP 2 VBIAS 1 VBIAS 2 VREF GND AGND FSADJ 1 FSADJ 2
RSET 1 RSET 2 R
LOAD
Digital Power Plane Analog Power Plane C6 C7 - C9 L1 3.3 V (VCC)
VDDMAX
C15
C1
C10 - C14
C2
C3
C4
Ground (Power Supply Connector)
RLOAD RLOAD RLOAD RLOAD RLOAD
DACA DACB DACB DACB DACB DACB LPF
C18
P P P P P P RF Modulator/CVBS Out
22 pF
75
LPF LPF/RF MOD LPF LPF/RF MOD LPF LPF To Video Connector
Buffer
P
CVBS
VAA P Schottky Diode To Filter Schottky Diode GND
TRAP L2 C16 C17 1.8 H 270 pF 330 pF
82
RF Modulator ZIN = 1 K(2)
DAC Output
Audio
NOTE(S):
(1) This
pin must be connected to 5 V if 5 V tolerance is required. If only 3.3 V tolerance is required, this pin should be connected to VAA. (2) Some modulators may require AC coupling capacitors (10 F). 3. For a typical parts list, see Table 4-1.
861_035
4-2
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
4.0 Applications
4.1 PC Board Considerations
4.1.3 Device Decoupling
For optimum performance, all decoupling capacitors should be located as close as possible to the device, and the shortest possible leads should be used to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radial lead ceramic capacitors can be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values chosen have self-resonance above the pixel clock frequency.
4.1.4 Power Supply Decoupling
The best power supply performance is obtained with 0.1 F ceramic capacitors decoupling each group of power pins to ground. Place the capacitors as close as possible to the device power pins and ground pins and connect with short, wide traces. Table 4-1 is a typical parts list. The 47 F capacitor illustrated in Figure 4-1 is for low-frequency power supply ripple; the 0.1 F capacitors are for high-frequency power supply noise rejection. A linear regulator is recommended to filter the analog power supply if the power supply noise is excessive. This is especially important when using a switching power supply.
Figure 4-2. Recommended Crystal Circuit
Bt860/861 C19 XTI
XTAL XTO
R1
C20
NOTE(S): For typical parts list, see Table 4-1.
861_039
D860DSA
Conexant
4-3
4.0 Applications
4.1 PC Board Considerations
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 4-1. Typical Parts List
Location
C1, C15 C16 C17 C18 C19 C2 C20 C3-14 L1 L2 P R1 Rload RSET1, RSET2 TRAP
Description
47 F Capacitor 5% 270 pF Ceramic Capacitor 5% 330 pF Ceramic Capacitor 5% 22 pF Ceramic Capacitor 5% 33 pF Ceramic Capacitor 20% 1.0 F Ceramic Capacitor 5% 27 pF Ceramic Capacitor 0.1 F Ceramic Capacitor Ferrite Bead-Surface Mount 5% 1.8 H Inductor Dual Schottky Diodes 1 M Resistor 1% 75 Metal Film Resister 1% 301 Metal Film Resistor Ceramic Resonator
Vendor
Mallory AVX AVX AVX AVX AVX AVX Erie Fair-Rite KOA HP DALE DALE Dale Murata
Part Number
CSR13F476KM 08055A271JATMA 08055A331JATMA 08055A220JATMA 08055A330JATMA 08053G105ZAT2A 08055A270JATMA RPE112Z5U104M50V 2743021447 KL32TEIR8J BAT54F CRCW08051004FRT1 CRCW080575ROFRT1 CRCW08053010FRT1 TPSx.xMJ (where x.x = sound carrier frequency in MHz) H1431818-18
XTAL
50 ppm, 14.31818 MHz Fundamental Crystal
Hooray
NOTE(S): Vendor numbers are listed only as a guide. Substitution of devices with similar
characteristics will not affect BT860/861 performance.
4.1.5 COMP Decoupling
The COMP1 and COMP2 pins should be decoupled to the closest VAA pin with a 0.1 F ceramic capacitor. Greater low-frequency supply noise will require a larger value. The COMP1 and COMP2 capacitors must be as close as possible to the COMP1, COMP2, and VAA pins.
4.1.6 VREF Decoupling
A 1.0 F ceramic capacitor should be used to decouple VREF to AGND.
4.1.7 VBIAS Decoupling
A 0.1 F ceramic capacitor should be used to decouple VBIAS1 and VBIAS2 to AGND.
4-4
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
4.0 Applications
4.1 PC Board Considerations
4.1.8 Digital Signal Interconnect
The digital inputs to the Bt860/861 should be isolated from the analog outputs and other analog circuitry as much as possible and should not overlay the analog power plane. Most noise on the analog outputs is caused by excessive edge rates (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs coupling into the analog signals. Ringing can be reduced by damping the line with a series resistor (30-300 ). Because feed-through noise is proportional to the digital edge rates, lower-speed logic (3-5 ns edge rates) should be used whenever possible. Route the digital signals at 90-degree angles to any analog signals.
4.1.9 Analog Signal Interconnect
Locate the Bt860/861 as close as possible to the output connectors to minimize noise pickup and reflections caused by impedance mismatch. The video output signals should overlay the ground plane. The analog outputs are susceptible to crosstalk from digital lines; digital traces must not be routed under or adjacent to the analog output traces. For maximum performance, the analog video output impedance, cable impedance, and load impedance should be identical. The load resistor connection between the video outputs and AGND should be as close as possible to the Bt860/861 to minimize reflections. Turn off all unused analog outputs by setting the applicable EN_DAC_x register bit to 0.
4.1.10 ESD and Latchup Considerations
Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms ranging from catastrophic failure to erratic device behavior with leaky inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. DAC power decoupling networks with large time constants should be avoided; they could delay VAA and VDD power to the device. Ferrite beads must be used only for analog power VAA decoupling. Inductors cause a time constant delay that induces latchup, and should not be substituted for ferrite beads. Latchup can be prevented by ensuring that all power pins are at the same potential, all GND pins are at the same potential, and that the VAA and VDD supply voltages are applied before the signal pin voltages. The correct power-up sequence ensures that any signal pin voltage will never exceed the power supply voltage.
D860DSA
Conexant
4-5
4.0 Applications
4.1 PC Board Considerations
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
4-6
Conexant
D860DSA
5
5.0 Serial Programming Interface and Registers
5.1 Serial Interface
The Bt860/861 uses a 2-wire serial programming interface to program the device registers. The interface operates at 3.3 V or 5.0 V input levels. Figure 5-1 illustrates the timing relationship between Serial Interface Data (SID) and Serial Interface Clock (SIC) lines. If the bus is not being used, both SID and SIC lines must be pulled high.
Figure 5-1. Serial Programming Interface Timing Diagram
Subsequent Bytes and Acknowledge Interpreted as Data Values for Auto-Incrementing Subaddress Locations
SIC
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
MSB
LSB
SID
Start Condition
(1)
(1)
(1)
Slave Address
Subaddress
Data
NOTE(S):
(1)
Acknowledge generated by Bt860/861.
861_024
D860DSA
Conexant
Stop Condition
5-1
5.0 Serial Programming Interface and Registers
5.1 Serial Interface
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Every data word put onto the SID line must be 8 bits long (MSB first), followed by an acknowledge bit, generated by the receiving device. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always the slave address byte. If this is the device address, the device generates an acknowledge signal by pulling the SID line low during the ninth clock pulse. The eighth bit of the address byte is the read/write* bit (high = read from the addressed device, low = write to the addressed device). Data bytes are always acknowledged during the ninth clock pulse by the addressed device.
NOTE:
During the acknowledge period, the master device must leave the SID line high.
Premature termination of the data transfer is allowed by generating a stop condition at any time. When this happens, the Bt860/861 remains in the state defined by the last complete data byte transmitted, and any master acknowledge subsequent to reading the chip ID (subaddress 0x89) is ignored.
5.1.1 Device Address
The device address is configurable by the state of the ALTADDR pin at reset. If SCART functionality is not desired, the ALTADDR pin may be tied directly to power or ground to configure this address. Otherwise, the address should be configured through a soft-tie resistor to power or ground. Table 5-1 lists how the ALTADDR pin configures the device address.
Table 5-1. Serial Address Configuration
ALTADDR
0 1
Device Address
7'b1000101 7'b1000100
Device Address Byte for Writes
0x8A 0x88
Device Address Byte for Reads
0x8B 0x89
5.1.2 Writing Data
A write transaction involves sending the device address byte with the read/write* bit low, and following it with one or more bytes. The first byte following the device address byte is always assumed to be a register subaddress, and sets an internal register subaddress pointer. This address is an 8-bit quantity, thus allowing the addressing of up to 256 byte-wide registers. If a second byte follows the device address byte, it is assumed to be the write data for the register indexed in the first byte. Any subsequent bytes are assumed to be write data for registers whose address follows in ascending order, as the internal subaddress pointer is incremented at the completion of each register write. The state of this internal address pointer upon exiting a write transaction is used for any read transactions that follow. Figure 5-2 illustrates a typical register write sequence. 1. Master transmits the device address with the read/write* bit low. 2. Master transmits the desired register subaddress. 3. Master transmits the register write data byte. 4. Subsequent registers are written until a stop condition is detected.
5-2
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.1 Serial Interface
Figure 5-2. Serial Programming Interface Typical Write Sequence
Chip Write Address 88 or 8A Optional Sequential Write May be Repeated S = Start Condition P = Stop Condition A = Acknowledge From Master From Bt860/861
861_036
S
A
Sub Address
A
Data
A
Data
A
P
5.1.3 Reading Data
A read transaction involves sending the device address byte with the read/write* bit high, and receiving one or more bytes after changing the direction of the bus. The first byte returned after the device address byte is the contents of the last indexed register subaddress. Any subsequent data bytes read come from registers whose address follows in ascending order as the internal subaddress pointer is incremented at the completion of every read. The initial register subaddress depends on the state of the pointer at the end of the last write transaction. Because writing even one data byte to a register will increment the subaddress pointer, typically one would want to precede a read with a write transaction that sends only the register subaddress byte. Figure 5-3 illustrates a typical register read sequence.
1. 2. 3. 4. 5. 6.
Master transmits the device address with the read/write* bit low. Master transmits the desired register subaddress. Master generates repeat start. Master transmits the device address with the read/write* bit high. Slave (Bt860/861) transmits the data byte to master. Subsequent registers are read until a stop condition is detected.
Figure 5-3. Serial Programming Interface Typical Read Sequence
S Chip Write Address 88 or 8A A Sub Address A Sr Chip Read Address 89 or 8B A Data A Data NA P
Optional Sequential Read May be Repeated S = Start Condition P = Stop Condition A = Acknowledge Sr = Repeat Start Condition NA = Not Acknowledged From Master From Bt860/861
861_037
D860DSA
Conexant
5-3
5.0 Serial Programming Interface and Registers
5.2 Internal Registers
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.2 Internal Registers
Registers provide direct control and status of the part. These registers are accessed by the serial programming interface described in this section. Table 5-2 provides a register bit map. Table 5-3 lists the alpha-sorted register index. Section 5.4 gives bit descriptions and detailed programming information. All registers are read/write unless otherwise indicated, and are set to default values following a software, power, and pin reset. A software reset is always performed at power-up, and when register bit SRESET (1B[7]) is set to 1.
5.2.1 Register Bit Map
Table 5-2. Register Bit Map (1 of 4)
Sub Default addr Values(1)
00(2) 01(2) 02(2) 03(2) 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14
D7
D6
D5
Reserved(3)
D4
VERSION[2:0]
D3
D2
D1
Reserved(3)
D0
4C or 0C ID[1:0] -- -- 00 B4 06 C8 02 7E 90 54 0C 01 13 F1 00 00 00 02 8C AF
MONSTAT_F MONSTAT_E MONSTAT_D MONSTAT_C MONSTAT_B MONSTAT_A XDS_STAT FIELD_CNT[3:0] Reserved(3) HCLK[7:0] Reserved(4) HACTIVE[7:0] Reserved(4) AHSYNC_WIDTH[7:0] HBURST_BEG[7:0] HBURST_END[7:0] HBLANK[7:0] Reserved(4) VBLANK[7:0] VACTIVE[7:0] Reserved(4) HSYNC_OFF[7:0] Reserved(4) HSYNC_WIDTH[7:0] PLL_FRACT[7:0] PLL_FRACT[15:8] HBLANK[9:8] HACTIVE[9:8] HCLK[11:8] VLOCK_ERR PLL_LOCK
CC_STAT
FIFO_UNDER FIFO_OVER
VACTIVE[8]
HSYNC_OFF[9:8]
5-4
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 5-2. Register Bit Map (2 of 4)
Sub Default addr Values(1)
15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 0F 10 10 3F 80 80 00 C1 01 E5 75 C1 89 9A 80 80 80 1F 7C F0 21 13 DA 4B 28 85 A3 05 9F 04 A3 05 9F
5.0 Serial Programming Interface and Registers
5.2 Internal Registers
D7
D6
D5
D4
PLL_INT[4:0] SETUP PAL
D3
D2
D1
D0
PLL_FRACT [18:16] SC_RESET VSYNC_DUR 625LINE
FM DCHROMA
NI ECBAR EN_DAC_B
SLAVE ECLIP EN_DAC_A
CHROMA_BW BLUE_FLD
OUTMODE[2:0] EN_DAC_F EN_DAC_E FIELDI EN_DAC_D BLANKI
YDELAY[2:1] PCLK_SEL VSYNCI
EN_DAC_C
HSYNCI
BLK_IGNORE PCLK_EDGE FLDMODE EN_656 AUTO_CHK VIDFIELDI CLKO_DIS PROG_SC SC_PATTERN
BLENDMODE ALPHAMODE[1:0] SRESET XL_VRI DIS_XTAL FIELD_ID LC_RST
OVRLAY_SEL VIDEO_SEL
CVBSD_INV PKFIL_SEL[1:0] LOCK VIDVACTI DIS_PLL VIDHACTI BY_PLL
CHECK_STAT SLEEP VIDVALIDI EACTIVE XL_LOCK CROSSFILT
DIS_SCADJ SYNC_CFG
SYNC_AMP[7:0] BURST_AMP[7:0] M_CR[7:0] M_CB[7:0] M_Y[7:0] M_COMP_D[7:0] M_COMP_F[7:0] M_COMP_E[7:0] M_SC_DR[7:0] M_SC_DR[15:8] M_SC_DR[23:16] M_SC_DR[31:24] M_SC_DB[7:0] M_SC_DB[15:8] M_SC_DB[23:16] M_SC_DB[31:24] SC_AMP[7:0] DR_MAX[7:0] Reserved(4) DR_MIN[7:0] Reserved(4) DB_MAX[7:0] Reserved(4) DB_MIN[7:0] DB_MAX[10:8] DR_MIN[10:8] DR_MAX[10:8]
D860DSA
Conexant
5-5
5.0 Serial Programming Interface and Registers
5.2 Internal Registers
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 5-2. Register Bit Map (3 of 4)
Sub Default addr Values(1)
36 37 38 39 3A 3B 3C 3D-3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 04 00 00 50 FA 00 10 00 80 80 80 80 4A 01 8C 09 00 44 -- -- -- 39 01 07 00 00 00 00 00 00 00 00 00
D7
Reserved(4) Y_OFF[7:0] PHASE_OFF[7:0]
D6
D5
D4
D3
D2
DB_MIN[10:8]
D1
D0
ALPHA_LUT_1[3:0] ALPHA_LUT_3[3:0] HUE_ADJUST[7:0]
VIDCLK_EDGE YDELAY[0]
ALPHA_LUT_0[3:0] ALPHA_LUT_2[3:0]
XL_MDSEL[1:0]
XL_SATEN
FIL_SEL
SCART_SEL[1:0]
Reserved XDSB1[7:0] XDSB2[7:0] CCB1[7:0] CCB2[7:0] CCSTART[7:0] Reserved(4) CCADD[7:0] Reserved(4) Reserved(4) XDSSEL[3:0] EWSSF2 WSDAT[12:5] WSDAT[20:13] TTXHS[7:0] Reserved(4) TTXHE[7:0] Reserved(4) TTXBF1[7:0] Reserved(4) TTXEF1[7:0] Reserved(4) TTXXBF2[7:0] Reserved(4) TTXEF2[7:0] Reserved(4) TTXEF2[8] TTXXBF2[8] TTXEF1[8] TTXBF1[8] TTXHE[10:8] TTXHS[10:8] EWSSF1 Reserved(4) SQUARE CCSEL[3:0] WSDAT[4:1] CCADD[11:8] ECCGATE EXDS ECC CCSTART[8]
5-6
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 5-2. Register Bit Map (4 of 4)
Sub Default addr Values(1)
59 5A 5B 5C 5D 5E 5F 60-6F 70 71 72 73 74-FF 02 00 00 7F 0 0 7F -- 80 01 80 72 00
5.0 Serial Programming Interface and Registers
5.2 Internal Registers
D7
Reserved(4) TTX_DIS[7:0] TTX_DIS[15:8] MULT_UU[7:0] MULT_VU[7:0] MULT_UV[7:0] MULT_VV[7:0]
D6
D5
D4
D3
D2
D1
TXRM TXE
D0
Reserved. Do not write to these registers. LC_FIFOWIN[7:0] Reserved(4) LC_MAXOFF[7:0] XL_GAIN[3:0] Reserved. Do not write to these registers. XL_SAT[3:0]
LC_FIFOWIN[8]
NOTE(S):
(1) (2)
Default values in this table are hexadecimal. These registers are read only. (3) These bits return zero when read. (4) Reserved bits should be set to zero when written and will return zero when read.
D860DSA
Conexant
5-7
5.0 Serial Programming Interface and Registers
5.3 Register Index
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.3 Register Index
Table 5-3. Register Index (1 of 5)
Field
625LINE
AHSYNC_WIDTH[7:0]
Default Value(1)
0 7E 0 5 A F 00 0 0 1 0 0 75 0 -- 98C 80 80 4 14A -- 0 0 1 0 5A3 49F 0 0 0 0
Register
16[5] 08[7:0] 39[3:0] 39[7:4] 3A[3:0] 3A[7:4] 1A[6:5] 1B[2] 19[3] 1A[7] 19[2] 17[6] 1F[7:0] 1D[3] 01[0] 47[3:0] 46[7:0] 42[7:0] 43[7:0] 49[3:0] 45[0] 44[7:0] 1B[1] 17[7] 1D[2] 1D[0] 1B[5] 34[2:0] 33[7:0] 36[2:0] 35[7:0] 17[2] 1D[4] 1D[6] 1D[7]
Description
Number of Lines per Frame Analog Horizontal Sync Width Alpha Blend Lookup Table Elements 0 Alpha Blend Lookup Table Elements 1 Alpha Blend Lookup Table Elements 2 Alpha Blend Lookup Table Elements 3 Alpha Select Automatic Monitor Status Checking BLANK* Polarity Control Blend Select BLANK Control Blue Field Multiplication Factor for the Colorburst Amplitude for NTSC/PAL Bypass PLL Closed Captioning Buffer Status Closed Captioning or Extended Data Services DTO Increment First Byte of Closed Captioning Information Second Byte of Closed Captioning Information Line Position of Closed Captioning Content Closed Captioning or Extended Data Services Start Placement Manual Monitor Status Checking Chrominance Bandwidth CLKO Disable SECAM Cross Color Filter Invert CVBS_DLY Outputs Upper Boundary for Db Frequency Deviation in SECAM Lower Boundary for Db Frequency Deviation in SECAM Disable Chrominance Sleep PLL Disable Automatic Subcarrier Adjust Disable Crystal Circuitry
ALPHA_LUT_0[3:0] ALPHA_LUT_1[3:0] ALPHA_LUT_2[3:0] ALPHA_LUT_3[3:0] ALPHAMODE[1:0] AUTO_CHK BLANKI BLENDMODE BLK_IGNORE BLUE_FLD BURST_AMP[7:0] BY_PLL CC_STAT CCADD[11:0] CCB1[7:0] CCB2[7:0] CCSEL[3:0] CCSTART[8:0] CHECK_STAT CHROMA_BW CLKO_DIS CROSSFILT CVBSD_INV DB_MAX[10:0] DB_MIN[10:0] DCHROMA DIS_PLL DIS_SCADJ DIS_XTAL
5-8
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 5-3. Register Index (2 of 5)
Field
DR_MAX[10:0] DR_MIN[10:0] EACTIVE ECBAR ECC ECCGATE ECLIP EN_656 EN_DAC_A EN_DAC_B EN_DAC_C EN_DAC_D EN_DAC_E EN_DAC_F EWSSF1 EWSSF2 EXDS FIELD_CNT[3:0] FIELD_ID FIELDI FIFO_OVER FIFO_UNDER FIL_SEL FLDMODE FM HACTIVE[9:0] HBLANK[9:0] HBURST_BEG[7:0] HBURST_END[7:0] HCLK[11:0] HSYNC_OFF[9:0] HSYNC_WIDTH[7:0] HSYNCI HUE_ADJUST ID[1:0]
5.0 Serial Programming Interface and Registers
5.3 Register Index
Default Value(1)
5A3 49F 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 -- 0 0 -- -- 0 0 0 2C8 10C 90 54 6B4 000 02 0 00 00 or 01
Register
30[2:0] 2F[7:0] 32[2:0] 31[7:0] 1D[1] 17[1] 48[0] 48[2] 17[0] 1A[2] 18[0] 18[1] 18[2] 18[3] 18[4] 18[5] 4A[6] 4A[7] 48[1] 02[7:4] 1B[6] 19[4] 02[0] 02[1] 3C[2] 19[0] 16[2] 07[1:0] 06[7:0] 0C[1:0] 0B[7:0] 09[7:0] 0A[7:0] 05[3:0] 04[7:0] 11[1:0] 10[7:0] 12[7:0] 19[5] 3B[7:0] 00[7:6]
Description
Upper Boundary for Dr Frequency Deviation in SECAM Lower Boundary for Dr Frequency Deviation in SECAM Enable Active Video Enable Internal Color Bars Enable Closed Captioning Closed Captioning Gating Enable Clipping Enable 656 Code Translation Enable DAC A Enable DAC B Enable DAC C Enable DAC D Enable DAC E Enable DAC F Enable WSS or CGMS Function on Field 1 Enable CGMS Function on Field 2 Enable Extended Data Services Field Number Enable SECAM Bottleneck Pulses FIELD Polarity Control FIFO Overflow Status FIFO Underflow Status Filter Select Field Tolerance FM Modulation Number of Active Pixels Per Line Horizontal Blanking Length Beginning of Burst End of Burst Number of System Clocks Per Line HSYNC* Offset HSYNC* Width HSYNC* Polarity Control Hue Adjustment by Subcarrier Shift Part Identification
D860DSA
Conexant
5-9
5.0 Serial Programming Interface and Registers
5.3 Register Index
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 5-3. Register Index (3 of 5)
Field
LC_FIFOWIN[8:0] LC_MAXOFF[7:0] LC_RST LOCK M_CB[7:0] M_COMP_D[7:0] M_COMP_F[7:0] M_COMP_E[7:0] M_CR[7:0] M_SC_DB[31:0]
Default Value(1)
180 80 1 0 89 80
Register
71[0] 70[7:0] 72[7:0] 1C[6] 1C[5] 21[7:0] 23[7:0] 24[7:0] 25[7:0] 20[7:0] 2D[7:0] 2C[7:0] 2B[7:0] 2A[7:0] 29[7:0] 28[7:0] 27[7:0] 26[7:0] 22[7:0] 01[2] 01[3] 01[4] 01[5] 01[6] 01[7] 5C[7:0] 5D[7:0] 5E[7:0] 5F[7:0] 16[1] 17[5:3] 1A[4] 16[3] 19[1] 19[7] 38[7:0] 1B[4:3] 15[7:5] 14[7:0] 13[7:0] 15[4:0] 02[2] 1A[1]
Description
FIFO Window Max Adjustment Locking Reset Start VID Path Locking Multiplication Factor for the Cb Component Prior to Modulation Multiplication Factor for the Component at DAC D Multiplication Factor for the Component at DAC F Multiplication Factor for the Component at DAC E Multiplication Factor for the Cr Component Prior to Modulation Subcarrier Increment for Db for SECAM
C1 284BDA13
M_SC_DR[31:0]
21F07C1F
Subcarrier Increment for NTSC/PAL or Dr for SECAM
M_Y[7:0] MONSTAT_A MONSTAT_B MONSTAT_C MONSTAT_D MONSTAT_E MONSTAT_F MULT_UU MULT_UV MULT_VU MULT_VV NI OUTMODE[2:0] OVRLAY_SEL PAL PCLK_EDGE PCLK_SEL PHASE_OFF[7:0] PKFIL_SEL[1:0] PLL_FRACT[18:0]
9A --
Luminance Multiplication Factor (contrast control) DAC A Connection Status DAC B Connection Status DAC C Connection Status DAC D Connection Status DAC E Connection Status DAC F Connection Status Chrominance Matrix Multiplier Chrominance Matrix Multiplier Chrominance Matrix Multiplier Chrominance Matrix Multiplier Non-Interlace Enable DAC Output Format Control Overlay Select Phase Alternation Pixel Clock Edge Sample Select Pixel Clock (system clock) Select Subcarrier Phase Offset (for SC - H Phase Adjustments) Luminance Peaking Filter Gain Selection Fractional Portion of the PLL Multiplier
7F 00 00 7F 0 010 0 0 0 1 00 00 OAF8C
PLL_INT[4:0] PLL_LOCK PROG_SC
0F 1 0
Integer Portion of the PLL Multiplier PLL Lock Status Bit SECAM Subcarrier Control
5-10
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 5-3. Register Index (4 of 5)
Field
SC_AMP[7:0] SC_PATTERN SC_RESET SCART_SEL SETUP SLAVE SLEEP SQUARE SRESET SYNC_AMP[7:0] SYNC_CFG TTX_DIS[15:0] TTXBF1[8:0] TTXBF2[8:0] TTXEF1[8:0] TTXEF2[8:0] TTXHE[10:0] TTXHS[10:0] TXE TXRM VACTIVE[8:0] VBLANK[7:0] VERSION[2:0] VIDCLK_EDGE VIDEO_SEL VIDFIELDI VIDHACTI VIDVACTI VIDVALIDI VLOCK_ERR VSYNC_DUR VSYNCI
5.0 Serial Programming Interface and Registers
5.3 Register Index
Default Value(1)
85 0 0 00 1 0 0 0 0 E5 0 0000 000 000 000 000 007 139 0 1 0F1 13 011 0 0 0 0 0 0 -- 0 0
Register
2E[7:0] 1A[0] 16[7] 3C[1:0] 16[4] 16[0] 1B[0] 4A[4] 1B[7] 1E[7:0] 1D[5] 5B[7:0] 5A[7:0] 52[0] 51[7:0] 56[0] 55[7:0] 54[0] 53[7:0] 58[0] 57[7:0] 50[2:0] 4F[7:0] 4E[7:0] 4D[2:0] 59[0] 59[1] 0F[0] 0E[7:0] 0D[7:0] 00[4:2] 3C[7] 1A[3] 1C[2] 1C[3] 1C[4] 1C[1] 02[3] 16[6] 19[6]
Description
Multiplication Factor for the SECAM Subcarrier Amplitude SECAM Phase Sequence Subcarrier Reset SCART Selection Options Setup Master/Slave Control Sleep Square Pixel or CCIR Timing Select for Teletext and WSS Software Reset Sync Tip to Blank Amplitude Sync Configuration Teletext Disable by Line Teletext Start Line for Field 1 Teletext Start Line for Field 2 Teletext End Line for Field 1 Teletext End Line for Field 2 TTXREQ Falling Edge TTXREQ Rising Edge Teletext Enable TTXREQ Configuration Number of Active Lines per Field Vertical Blanking Length Version Number for the Part VIDCLK Edge Sample Select Video Select VIDFIELD Polarity Control VIDHACT Polarity Control VIDVACT Polarity Control VIDVALID Polarity Control VID Port Locking Status Analog and Digital Vertical SYNC Duration VSYNC* Polarity Control
D860DSA
Conexant
5-11
5.0 Serial Programming Interface and Registers
5.3 Register Index
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 5-3. Register Index (5 of 5)
Field
WSDAT[20:1]
Default Value(1)
--
Register
4C[7:0] 4B[7:0] 4A[3:0] 01[1] 40[7:0] 41[7:0] 49[7:4] 73[7:4] 1C[0] 3C[5:4] 73[3:0] 3C[3] 1C[7] 37[7:0] 18[7:6] 3C[6]
Description
WSS and CGMS Data Bits
XDS_STAT XDSB1[7:0] XDSB2[7:0] XDSSEL[3:0] XL_GAIN[3:0] XL_LOCK XL_MDSEL[1:0] XL_SAT[3:0] XL_SATEN XL_VRI Y_OFF[7:0] YDELAY[2:0]
NOTE(S):
(1)
-- 80 80 4 7 1 01 2 0 1 00 000
Extended Data Services Buffer Status First Byte of Extended Data Services Information Second Byte of Extended Data Services Information Line Position of Extended Data Services Content Accelerated Locking Gain Accelerated Locking Accelerated Locking Mode Select Accelerated Locking Saturation Accelerated Locking Saturation Enable Accelerated Locking Vertical Realignment Initiation Luminance Level Offset (brightness control) Luma Delay in 1/2 Pixel Increments for CVBS_DLY Outputs
Default values in this table refer to hexadecimal values if the register field contains four or more bits; otherwise the value is binary. 2. Internal timing and the values programmed into the registers reference the analog VSYNC pulse (OV) as line #1 (see Figures 3-1 and 3-2). 3. System clock = FCLK = 2x luminance sample frequency.
5-12
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
5.4 Register Detail
NOTE(S):
(1) Internal timing and the values programmed into the registers reference the analog VSYNC pulse (OV) as line #1 (see Figures 3-1 and 3-2). 2. System clock = FCLK = 2x luminance sample frequency.
Register 00
Register 00 Default Value 4C or 0C D7 ID[1:0] D6 D5 Reserved D4 D3 VERSION[2:0] D2 D1 Reserved D0
This register is read only. Reserved bits return zero when read.
ID[1:0]
Part Identification 00 = Bt860 01 = Bt861
VERSION[2:0]
Version Number for the Part. Current version returns 011.
Register 01
Register 01 Default Value -- D7 MONSTAT_F D6 MONSTAT_E D5 MONSTAT_D D4 MONSTAT_C D3 MONSTAT_B D2 MONSTAT_A D1 XDS_STAT D0 CC_STAT
This register is read only.
MONSTAT_F MONSTAT_E MONSTAT_D MONSTAT_C MONSTAT_B MONSTAT_A
DAC F Connection Status DAC E Connection Status DAC D Connection Status DAC C Connection Status DAC B Connection Status DAC A Connection Status 1 = Device connected to DAC output. 0 = No device connected to DAC output.
XDS_STAT
Extended Data Services Buffer Status 0 = Both XDSB1 and XDSB2 values have been encoded. 1 = Data has been written to the Extended Data Services registers and is not yet encoded.
CC_STAT
Closed Captioning Buffer Status 0 = Both CCB1 and CCB2 values have been encoded.
D860DSA
Conexant
5-13
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 02
Register 02 Default Value 04 D7 D6 D5 D4 D3 VLOCK_ERR D2 PLL_LOCK D1 FIFO_UNDER D0 FIFO_OVER
FIELD_CNT[3:0]
This register is read only.
FIELD_CNT[3:0]
Field Number 000 indicates the first field.
VLOCK_ERR
VID Port Locking Status High if VID port input frequency exceeds tracking range, as programmed by LC_MAXOFF.
PLL_LOCK
PLL Lock Status Bit 0 = Unable to lock to desired PLL frequency. 1 = PLL is able to lock to desired frequency.
FIFO_UNDER
FIFO Underflow Status High if VID port FIFO underflows. Resets to zero on write.
FIFO_OVER
FIFO Overflow Status High if VID port FIFO overflows. Resets to zero on write.
Register 04-05
Register 04 05 Default Value B4 06 Reserved D7 D6 D5 D4 HCLK[7:0] HCLK[11:8] D3 D2 D1 D0
Reserved bits should be set to zero when written and will return zero when read.
HCLK[11:0]
Number of System Clocks Per Line
Register 06-07
Register 06 07 Default Value C8 02 D7 D6 D5 D4 D3 D2 D1 D0
HACTIVE[7:0]
Reserved
HACTIVE[9:8]
Reserved bits should be set to zero when written and will return zero when read.
HACTIVE[9:0]
Number of Active Pixels Per Line
5-14
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 08
Register 08 Default Value 7E D7 D6 D5 D4 D3 D2 D1 D0
AHSYNC_WIDTH[7:0]
AHSYNC_WIDTH[7:0]
Analog Horizontal Sync Width Measured in system clock cycles, from 50% points of sync pulse.
Register 09
Register 09 Default Value 90 D7 D6 D5 D4 D3 D2 D1 D0
HBURST_BEG[7:0]
HBURST_BEG[7:0]
Beginning of Burst 50% point of burst from the 50% point of the analog horizontal sync falling edge, measured in system clock cycles.
Register 0A
Register 0A Default Value 54 D7 D6 D5 D4 D3 D2 D1 D0
HBURST_END[7:0]
HBURST_END[7:0]
End of Burst 50% point of burst from the 50% point of the analog horizontal sync falling edge, measured in system clock cycles - 128.
D860DSA
Conexant
5-15
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 0B-0C
Register 0B 0C Default Value 0C 01 Reserved D7 D6 D5 D4 D3 D2 D1 D0
HBLANK[7:0] HBLANK[9:8]
Reserved bits should be set to zero when written and will return zero when read.
HBLANK[9:0]
Horizontal Blanking Length Determines the number of system clocks between 50% point of the leading edge of the analog horizontal sync, as well as the relationship between the leading edge of the pulse on the HSYNC* pin and active video. If HBLANK is even, the relationship between the register and horizontal blanking in the encoded waveform is:
HBLANK = (desired horizontal blanking in system clocks) + 14
If HBLANK is odd, the relationship is:
HBLANK = (desired horizontal blanking in system clocks) + 15
Because, in either case you will get an even horizontal blanking in the encoded video waveform, the only reason for having an odd HBLANK value is to align the active video window with the encoding data stream. The relationship between HBLANK and the position of active video on the P, OSD, and ALPHA pins is:
HBLANK = [(HSYNC* pin to active video) + 2 + HSYNC_OFF]
master mode
HBLANK = [(HSYNC* pin to active video) + 3] slave mode BLK_IGNORE bit = 1
Register 0D
Register 0D VBLANK[7:0] Default Value 13 D7 D6 D5 D4 D3 D2 D1 D0
VBLANK[7:0]
Vertical Blanking Length Line number of first active line (number of blank lines + 1), measured from (0V) vertical sync(1).
Register 0E-0F
Register 0E 0F Default Value F1 00 D7 D6 D5 D4 D3 D2 D1 D0
VACTIVE[7:0] Reserved VACTIVE[8]
Reserved bits should be set to zero when written and will return zero when read.
VACTIVE[8:0]
Number of Active Lines per Field
5-16
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 10-11
Register 10 11 Default Value 00 00 Reserved D7 D6 D5 D4 D3 D2 D1 D0
HSYNC_OFF[7:0] HSYNC_OFF[9:8]
Reserved bits should be set to zero when written and will return zero when read.
HSYNC_OFF[9:0]
HSYNC* Offset Defines the offset in system clocks of HSYNC* pulse relative to the internal horizontal sync in master mode. This value is twos complement so that: 000 1FF 200 3FF = = = = 0 clock delay 2047 clock delay 2048 clock advance 1 clock advance
Register 12
Register 12 Default Value 02 D7 D6 D5 D4 D3 D2 D1 D0
HSYNC_WIDTH[7:0]
HSYNC_WIDTH[7:0]
HSYNC* Width Width in system clocks of HSYNC* pulse in master mode.
Register 13-15
Register 13 14 15 Default Value 8C AF 0F PLL_FRACT [18:16] D7 D6 D5 D4 D3 D2 D1 D0
PLL_FRACT[7:0] PLL_FRACT[15:8] PLL_INT[4:0]
PLL_FRACT[18:0] PLL_INT[4:0]
Fractional Portion of the PLL Multiplier Integer Portion of the PLL Multiplier The range of the PLL multiplier is from 0.0 to 3.999999, and the minimum adjustment is 1.90734863 x 10-6. The equation to derive PLL frequency is:
Desired PLL frequency = [(XTAL freq / 8) x (PLL_INT + (PLL_FRACT / 219))]
D860DSA
Conexant
5-17
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 16
Register 16 SC_RESET Default Value 10 D7 SC_RESET D6 VSYNC_DUR D5 625LINE D4 SETUP D3 PAL D2 FM D1 NI D0 SLAVE
Subcarrier Reset 0 = Subcarrier phase reset at beginning of each color field sequence. 1 = Disable subcarrier reset.
VSYNC_DUR
Analog and Digital Vertical Sync Duration Specifies the duration of the digital vertical sync pulse and the duration of the analog pre-equalization, post-equalization, and serration pulses. 0 = 3 lines. 1 = 2.5 lines.
625LINE
Number of Lines per Frame 0 = 525-line format. 1 = 625-line format.
SETUP
Setup 0 = 7.5 IRE setup disabled. 1 = 7.5 IRE setup enabled.
PAL
Phase Alternation 0 = Disable phase alternation (NTSC and SECAM). 1 = Enable phase alternation (PAL).
FM
FM Modulation 0 = QAM chroma encoding (NTSC/PAL). 1 = FM chroma encoding (SECAM).
NI
Non-Interlace Enable 0 = Interlaced field operation. 1 = Non-interlaced field operation.
SLAVE
Master/Slave Control 0 = Generate video timing for other devices (master mode). 1 = Accept video timing from other devices (slave mode). (See also register bits EN656 and SYNC_CFG.)
5-18
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 17
Register 17 CHROMA_BW Default Value 10 D7 CHROMA_BW D6 BLUE_FLD D5 D4 OUTMODE[2:0] D3 D2 DCHROMA D1 ECBAR D0 ECLIP
Chrominance Bandwidth 0 = Normal chroma bandwidth. 1 = Wide chroma bandwidth. See filter plots in Section 3.2.2
BLUE_FLD
Blue Field 0 = Normal operation. 1 = Generate blue field.
OUTMODE[2:0]
DAC Output Format Control Controls format output on each DAC, as listed in the following table.
Bits 000 001 010 011 100 101 110 111
DAC A Y Y Y Y CVBS CVBS CVBS Y
DAC B C C C C CVBS_DLY CVBS_DLY CVBS_DLY C
DAC C CVBS CVBS CVBS Y CVBS CVBS CVBS CVBS
DAC D Y R CVBS_DLY Y Y R CVBS_DLY CVBS_DLY
DAC E V G CVBS C V G CVBS C
DAC F U B CVBS C U B CVBS Y
NOTE(S): CVBS_DLY is the composite video signal with the luminance component delayed as controlled by YDELAY.
DCHROMA
Disable Chrominance 0 = Normal operation. 1 = Disable chroma components.
ECBAR
Enable Internal Color Bars 0 = Normal operation. 1 = Enable color bars. See colorbar plots in Section 3.2.3.
ECLIP
Enable Clipping 0 = Normal operation. 1 = Enable clipping. DAC values less than 64 are made 63. This limit corresponds to roughly one-fourth of the sync height.
D860DSA
Conexant
5-19
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 18
Register 18 YDELAY[2:1] Default Value 3F D7 D6 D5 EN_DAC_F D4 EN_DAC_E D3 EN_DAC_D D2 EN_DAC_C D1 EN_DAC_B D0 EN_DAC_A
YDELAY[2:1]
MSBs of Luma Delay in Pixels for CVBS_DLY Outputs YDELAY[0] is in 1/2 pixel increments, at 3C[6]. 00 = No delay. 01 = Delay 1 pixel. 10 = Delay 2 pixels. 11 = Delay 3 pixels.
EN_DAC_F EN_DAC_E EN_DAC_D EN_DAC_C EN_DAC_B EN_DAC_A
Enable DAC F Enable DAC E Enable DAC D Enable DAC C Enable DAC B Enable DAC A 0 = Disable individual DAC output. 1 = Enable individual DAC output.
5-20
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 19
Register 19 PCLK_SEL Default Value 80 D7 PCLK_SEL D6 VSYNCI D5 HSYNCI D4 FIELDI D3 BLANKI D2 BLK_IGNORE D1 PCLK_EDGE D0 FLDMODE
Pixel Clock (system clock) Select State of FIELD pin during power-up determines the default value of PCLK_SEL. FIELD = 1 corresponds to PCLK_SEL = 0 as default, while FIELD = 0 corresponds to PCLK_SEL = 1 as default. If FIELD is not externally loaded, an internal pull-down sets FIELD = 0 at power-up. 0 = Use CLKIN as pixel clock source. 1 = Use PLL as pixel source (derived from XTI and XTO inputs).
VSYNCI
VSYNC* Polarity Control 0 = Active low VSYNC* pin. 1 = Active high VSYNC* pin.
HSYNCI
HSYNC* Polarity Control 0 = Active low HSYNC* pin. 1 = Active high HSYNC* pin.
FIELDI
FIELD Polarity Control 0 = A 1 on FIELD pin indicates an even field. 1 = A 1 on FIELD pin indicates an odd field.
BLANKI
BLANK* Polarity Control 0 = Active low BLANK* pin. 1 = Active high BLANK* pin.
BLK_IGNORE
Blank Control 0 = Use BLANK* pin to indicate the active pixel region in slave mode. 1 = Use HBLANK, HACTIVE, VACTIVE, and VBLANK registers to determine the active pixel region in slave mode.
PCLK_EDGE
Pixel Clock Edge Sample Select 0 = P, OSD, ALPHA, HSYNC*, VSYNC*, BLANK* data sampled at the rising edge of the system clock. 1 = P, OSD, ALPHA, HSYNC*, VSYNC*, BLANK* data sampled at the falling edge of the system clock.
FLDMODE
Field Tolerance 0 = A falling edge of VSYNC* that occurs within 1/4 of a scan line from the falling edge of HSYNC* indicates the beginning of odd field. A falling edge of VSYNC* that occurs within 1/4 scan line from the center of the line indicates the beginning of even field. 1 = A falling edge of VSYNC* that occurs during HSYNC* high indicates the beginning of odd field. A falling edge of VSYNC* that occurs during HSYNC* low indicates the beginning of even field.
D860DSA
Conexant
5-21
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 1A
Register 1A BLENDMODE Default Value 80 D7 BLENDMODE D6 D5 D4 OVRLAY_SEL D3 VIDEO_SEL D2 EN_656 D1 PROG_SC D0 SC_PATTERN
ALPHAMODE[1:0]
Blend Select 0 = Alpha control contained in Y[1:0] of port selected by OVRLAY_SEL. 1 = Alpha control contained in ALPHA[1:0] pins as described by ALPHAMODE [1:0] bits. See Table 2-1.
ALPHAMODE[1:0]
Alpha Select (effective only when BLENDMODE = 1) 00 = Disable Alpha blending. 01 = Use ALPHA[0] as 1-bit alpha blend value with look-up table value. 10 = Use ALPHA[1:0] as 2-bit alpha blend value with look-up table value. 11 = Use ALPHA[1:0] over two load clocks to form a 4-bit alpha blend value. See Table 2-1 and Figure 2-2.
OVRLAY_SEL
Overlay Select 0 = Select P[7:0] as overlay blend stream. 1 = Select OSD[7:0] as overlay blend stream. See Table 2-1.
VIDEO_SEL
Video Select 0 = Select P[7:0] as video blend stream. 1 = Select VID[7:0] as video blend stream. See Table 2-1.
EN_656
Enable 656 Code Translation 0 = Use HSYNC*, VSYNC*, and BLANK* for video timing information. 1 = Use embedded SAV/EAV codes as defined by ITU-R BT.656 specification from port P[7:0] as timing source. See Table 2-2.
PROG_SC
SECAM Subcarrier Control 0 = SECAM subcarrier is generated on lines 23-310 and 336-623. 1 = SECAM subcarrier is generated on the active lines defined by VBLANK and VACTIVE.
SC_PATTERN
SECAM Phase Sequence 0 = 0 0 180 0 0 180 SECAM subcarrier phase sequence. 1 = 0 0 0 180 180 180 SECAM subcarrier phase sequence.
5-22
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 1B
Register 1B SRESET Default Value 00 D7 SRESET D6 FIELD_ID D5 CVBSD_INV D4 D3 D2 AUTO_CHK D1 CHECK_STAT D0 SLEEP
PKFIL_SEL[1:0]
Software Reset 0 = Normal operation. 1 = Reset all serial programming registers to their default values.
FIELD_ID
Enable SECAM Bottleneck Pulses 0 = Suppress SECAM field synchronization signal. 1 = Enable SECAM synchronization signal (bottleneck pulses).
CVBSD_INV
Invert CVBS_DLY Outputs 0 = Normal operation. 1 = Invert CVBS_DLY video output on DACs with CVBS_DLY selected.
PKFIL_SEL[1:0]
Luminance Peaking Filter Selection If FIL_SEL = 0 00 = Filter 0 (Default). 01 = Filter 1 (1 dB gain). 10 = Filter 2 (2 dB gain). 11 = Filter 3 (3.5 dB gain).
Amplitude in dB 3 2 0 1 5 4 5 6 10 7 15 0
If FIL_SEL = 1 00 = Filter 4. 01 = Filter 5. 10 = Filter 6. 11 = Filter 7.
20 0 1 2 3 4 5 Frequency in MHz 6 7 8
861_040
AUTO_CHK
Automatic Monitor Status Checking 0 = Set the connection status bits (MONSTAT_A through MONSTAT_F) by writing to the CHECK_STAT bit. 1 = Check the connection status bits once per frame during the vertical blanking interval.
CHECK_STAT
Manual Monitor Status Checking Writing a 1 to this bit checks the connection status of the DACs. This is also automatically performed on any reset condition. This bit is automatically cleared.
SLEEP
Sleep 0 = Normal operation. 1 = Sleep mode. Power down all components except serial interface and PLL. System clock must be applied to wake up part.
D860DSA
Conexant
5-23
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 1C
Register 1C XL_VRI Default Value C1 D7 XL_VRI D6 LC_RST D5 LOCK D4 VIDVACTI D3 VIDHACTI D2 VIDFIELDI D1 VIDVALIDI D0 XL_LOCK
Accelerated Locking Vertical Realignment Initiation 0 = Disable Accelerated Locking Vertical Realignment Initiation. 1 = Enable Accelerated Locking Vertical Realignment Initiation. When accelerated VID path locking is enabled, a vertical realignment larger than 18 lines will initiate an accelerated locking adjustment.
LC_RST
Locking Reset 0 = Normal locking operation. 1 = Reset locking logic.
LOCK
Start VID Path Locking 0 = Disable VID path locking operation. 1 = Normal VID path locking operation.
VIDVACTI
VIDVACT Polarity Control 0 = Active high VIDVACT pin. 1 = Active low VIDVACT pin.
VIDHACTI
VIDHACT Polarity Control 0 = Active high VIDHACT pin. 1 = Active low VIDHACT pin.
VIDFIELDI
VIDFIELD Polarity Control 0 = A 1 on VIDFIELD pin indicates an even field. 1 = A 1 on VIDFIELD pin indicates an odd field.
VIDVALIDI
VIDVALID Polarity Control 0 = Active high VIDVALID pin. 1 = Active low VIDVALID pin.
XL_LOCK
Accelerated Locking 0 = Accelerated VID path locking off. 1 = Accelerated VID path locking mode.
5-24
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 1D
Register 1D DIS_XTAL Default Value 01 D7 DIS_XTAL D6 DIS_SCADJ D5 SYNC_CFG D4 DIS_PLL D3 BY_PLL D2 CLKO_DIS D1 EACTIVE D0 CROSSFILT
Disable Crystal Circuitry
0 = Normal operation. 1 = Power down crystal oscillator circuitry.
DIS_SCADJ
Disable Automatic Subcarrier Adjust
0 = Normal operation. 1 = Disable automatic subcarrier adjustment during locking.
SYNC_CFG
Sync Configuration 0 = VSYNC* and HSYNC* pins are configured as inputs. 1 = SLAVE and EN_656 registers determine the configuration of VSYNC* and HSYNC* pins. See Table 2-2.
DIS_PLL
Sleep PLL
0 = Enable PLL. 1 = Disable PLL.
For lower power consumption, disable PLL when not in use.
BY_PLL
Bypass PLL 1 = Bypass PLL. 0 = Channel XTAL clock through PLL.
CLKO_DIS
CLKO Disable 0 = Enable CLKO pin. 1 = Disable CLKO pin.
EACTIVE
Enable Active Video 0 = Black burst video output. 1 = Enable normal video output.
CROSSFILT
SECAM Cross Color Filter 0 = Apply SECAM luma cross color reduction filter. 1 = Bypass the filter (turn this off when using NTSC/PAL).
Register 1E
Register 1E Default Value E5 D7 D6 D5 D4 D3 D2 D1 D0
SYNC_AMP[7:0]
SYNC_AMP[7:0]
Sync Tip to Blank Amplitude Measured in LSB increments.
1 LSB = 1.25 V
D860DSA
Conexant
5-25
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 1F
Register 1F Default Value 75 D7 D6 D5 D4 D3 D2 D1 D0
BURST_AMP[7:0]
BURST_AMP[7:0]
Multiplication Factor for the Colorburst Amplitude for NTSC/PAL This register is ignored when using SECAM.
BURST_AMP = int {BURSTP-P x 210 / [(2 x 1.28 SincX + 0.5)]} if PAL = 0 BURST_AMP = int [0.707 x BURST P-P x 210 / (2 x 1.28 SincX + 0.5)] if PAL = 1 BURSTP-P = peak to peak burst amplitude in volts SincX = Sin[( x FSC / FCLK) / ( x FSC / FCLK)]
Register 20
Register 20 M_CR[7:0] Default Value C1 D7 D6 D5 D4 M_CR[7:0] D3 D2 D1 D0
Multiplication Factor for the Cr Component Prior to Modulation This register is used for colorspace conversion and saturation adjustment.
V = (Cr - 128) x M_CR / 256
Register 21
Register 21 M_CB[7:0] Default Value 89 D7 D6 D5 D4 M_CB[7:0] D3 D2 D1 D0
Multiplication Factor for the Cb Component Prior to Modulation This register is used for colorspace conversion and saturation adjustment.
U = (Cb - 128) x M_CB / 256
Register 22
Register 22 M_Y[7:0] Default Value 9A D7 D6 D5 D4 M_Y[7:0] D3 D2 D1 D0
Luminance Multiplication Factor (contrast control) M_Y ranges from 0-1.56, such that
M_Y[7:0] = 255 x multiplication factor 1.56
5-26
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 23-25
Register 23 24 25 Default Value 80 80 80 D7 D6 D5 D4 D3 D2 D1 D0
M_COMP_D[7:0] M_COMP_F[7:0] M_COMP_E[7:0]
M_COMP_D[7:0] M_COMP_F[7:0] M_COMP_E[7:0]
Multiplication Factor for the Component at DAC D Multiplication Factor for the Component at DAC F Multiplication Factor for the Component at DAC E
M_COMP_x = gain, where 0 < gain < 1.99 128 DAC output values are truncated to 1023.
Register 26-29
Register 26 27 28 29 Default Value 1F 7C F0 21 D7 D6 D5 D4 D3 D2 D1 D0
M_SC_DR[7:0] M_SC_DR[15:8] M_SC_DR[23:16] M_SC_DR[31:24]
M_SC_DR[31:0]
Subcarrier Increment for NTSC/PAL or Dr for SECAM
M_SC_DR[31:0] = int ((FSC / FCLK) x 232 + 0.5) where: FSC = the subcarrier frequency, FCLK = system clock (luminance sample frequency) Use relationship between HCLK and the subcarrier frequency as given in ITU-R BT.470. See Section 3.1.5.
Register 2A-2D
Register 2A 2B 2C 2D Default Value 13 DA 4B 28 D7 D6 D5 D4 D3 D2 D1 D0
M_SC_DB[7:0] M_SC_DB[15:8] M_SC_DB[23:16] M_SC_DB[31:24]
M_SC_DB[31:0]
Subcarrier Increment for Db for SECAM
M_SC_DB[31:0] = int ((FSC / FCLK) x 232 + 0.5) where: FSC = subcarrier frequency, FCLK = system clock (luminance sample frequency)
D860DSA
Conexant
5-27
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 2E
Register 2E SC_AMP[7:0] Default Value 85 D7 D6 D5 D4 D3 D2 D1 D0
SC_AMP[7:0]
Multiplication Factor for the SECAM Subcarrier Amplitude Measured in LSB increments.
SC_AMP = (Amp P-P) x (1023 / 1.28 x SincX) where Amp P-P is the peak to peak amplitude of the subcarrier. SincX = Sin[( x FSC / FCLK) / ( x FSC / FCLK)]
Register 2F-30
Register 2F 30 Default Value A3 05 D7 D6 D5 D4 D3 D2 D1 D0
DR_MAX[7:0]
Reserved
DR_MAX[10:8]
Reserved bits should be set to zero when written and will return zero when read.
DR_MAX[10:0]
Upper Boundary for Dr Frequency Deviation in SECAM
DR_MAX = (FMAX / FCLK) x 213
Register 31-32
Register 31 32 Default Value 9F 04 D7 D6 D5 D4 D3 D2 D1 D0
DR_MIN[7:0]
Reserved
DR_MIN[10:8]
Reserved bits should be set to zero when written and will return zero when read.
DR_MIN[10:0]
Lower Boundary for Dr Frequency Deviation in SECAM
DR_MIN = (FMIN / FCLK) x 213
5-28
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 33-34
Register 33 34 Default Value A3 05 D7 D6 D5 D4 D3 D2 D1 D0
DB_MAX[7:0]
Reserved
DB_MAX[10:8]
Reserved bits should be set to zero when written and will return zero when read.
DB_MAX[10:0]
Upper Boundary for Db Frequency Deviation in SECAM
DB_MAX = (FMAX / FCLK) x 213
Register 35-36
Register 35 36 Default Value 9F 04 Reserved D7 D6 D5 D4 D3 D2 D1 D0
DB_MIN[7:0] DB_MIN[10:8]
Reserved bits should be set to zero when written and will return zero when read.
DB_MIN[10:0]
Lower Boundary for Db Frequency Deviation in SECAM
DB_MIN = (FMIN / FCLK) x 213
Register 37
Register 37 Y_OFF[7:0] Default Value 00 D7 D6 D5 D4 Y_OFF[7:0] D3 D2 D1 D0
Luminance Level Offset (brightness control) The luminance level offset is referenced from black, and can be adjusted from -22.31 IRE (below black) to +22.14 IRE (above black). Active video will be added to the offset level. Y_OFF is a twos complement number, such that 0x00 = 0 IRE offset, 0x0F is +22.14 IRE offset, and 0x10 is -22.31 IRE offset.
Register 38
Register 38 Default Value 00 D7 D6 D5 D4 D3 D2 D1 D0
PHASE_OFF[7:0]
PHASE_OFF[7:0]
Subcarrier Phase Offset (for SC - H Phase Adjustments)
PHASE_OFF = 256 x phase offset 360 Phase offset ranges from 0 - 358.6.
D860DSA
Conexant
5-29
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 39-3A
Register 39 3A Default Value 50 FA D7 D6 D5 D4 D3 D2 D1 D0
ALPHA_LUT_1[3:0] ALPHA_LUT_3[3:0]
ALPHA_LUT_0[3:0] ALPHA_LUT_2[3:0]
ALPHA_LUT_0[3:0] ALPHA_LUT_1[3:0] ALPHA_LUT_2[3:0] ALPHA_LUT_3[3:0]
Alpha Blend Lookup Table Element 0 Alpha Blend Lookup Table Element 1 Alpha Blend Lookup Table Element 2 Alpha Blend Lookup Table Element 3 Alpha blend multiplier look-up table when using content-based blending. (BLEND MODE = 0) and when using pin-based blending in either 1-bit or 2-bit modes (BLEND MODE = 1 and ALPHAMODE = 01 or 10). If 1-bit pin-based alpha is used, a 0 on ALPHA[0] applies. ALPHA_LUT_0 and a 1 applies ALPHA_LUT_3.
Register 3B
Register 3B Default Value 00 D7 D6 D5 D4 D3 D2 D1 D0
HUE_ADJUST[7:0]
HUE_ADJUST[7:0]
Hue Adjustment by Subcarrier Shift
HUE_ADJUST = 256 x (Phase) 360 The hue adjustment ranges from 0 to 358.6
5-30
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 3C
Register 3C Default Value 10 D7 VIDCLK_EDGE D6 YDELAY[0] D5 D4 D3 XL_SATEN D2 FIL_SEL D1 SCART_SEL D0
XL_MDSEL[1:0]
VIDCLK_EDGE
VIDCLK EDGE Sample Select 0 = VID[7:0], VIDHACT, VIDVALT, VIDFIELD, VIDVALID are sampled on the rising edge of the VIDCLK. 1 = VID[7:0], VIDHACT, VIDVALT, VIDFIELD, VIDVALID are sampled on the falling edge of the VIDCLK.
YDELAY[0]
Luma Delay is System Clock Counts for CVBS_DLY Outputs. The MSBs for YDELAY are located in register 18. 0 = No delay. 1 = One system clock delay (1/2 pixel).
XL_MDSEL[1:0]
Accelerated Locking Mode Select 00 = Rapid frequency adjustment. 01 = Moderate frequency adjustment. 11 = Slow frequency adjustment.
XL_SATEN
Accelerated Locking Saturation Enable 00 = Disable accelerated locking saturation limit. 01 = Enable a saturation limit for the initial internal PLL adjustment of the accelerated locking sequence. The limit value is determined by the XL_SAT register field (73[3:0]).
FIL_SEL
Filters Select 0 = Enable peaking filters. 1 = Enable reduction filters. See PKFIL_SEL register bit description.
SCART_SEL
Scart Selection Options 00 = Disable SCART functionality on ALTADDR pin. 01 = ALTDDR pin is VBLANK signal. 10 = ALTDDR pin is composite sync signal. 11 = ALTDDR pin is composite blank signal. These signals are synchronized with the DAC outputs. See Figure 3-15.
Register 40-41
Register 40 41 XDSB1[7:0] Default Value 80 80 D7 D6 D5 D4 XDSB1[7:0] XDSB2[7:0] D3 D2 D1 D0
First Byte of Extended Data Services Information Data is encoded LSB first.
XDSB2[7:0]
Second Byte of Extended Data Services Information Data is encoded LSB first.
D860DSA
Conexant
5-31
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 42-43
Register 42 43 CCB1[7:0] Default Value 80 80 D7 D6 D5 D4 CCB1[7:0] CCB2[7:0] D3 D2 D1 D0
First Byte of Closed Captioning Information Data is encoded LSB first.
CCB2[7:0]
Second Byte of Closed Captioning Information Data is encoded LSB first.
Register 44-45
Register 44 45 Default Value 4A 01 D7 D6 D5 D4 D3 D2 D1 D0
CCSTART[7:0]
Reserved
CCSTART[8]
Reserved bits should be set to zero when written and will return zero when read.
CCSTART[8:0]
Closed Captioning or Extended Data Services Start Placement Number of clocks from leading edge of HSYNC* to start of Closed Captioning or Extended Data Services clock run-in. Default value is correct for 27 MHz operation.
Register 46-47
Register 46 47 Default Value 8C 09 D7 D6 D5 D4 CCADD[7:0] D3 D2 D1 D0
Reserved
CCADD[11:8]
Reserved bits should be set to zero when written and will return zero when read.
CCADD[11:0]
Closed Captioning or Extended Data Services DTO Increment Defines the width of Closed Captioning or Extended Data Services waveform. Default value is correct for 27 MHz operation.
5-32
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 48
Register 48 Default Value 00 D7 D6 D5 D4 D3 D2 ECCGATE D1 EXDS D0 ECC
Reserved
Reserved bits should be set to zero when written and will return zero when read.
ECCGATE
Closed Captioning Gating 0 = After current CC/XDS data is encoded, send Null data sequence until new data is written to registers. 1 = Repeat current CC/XDS data until new data is written to the registers.
EXDS
Enable Extended Data Services 0 = Disable Extended Data Services encoding. 1 = Enable Extended Data Services encoding.
ECC
Enable Closed Captioning 0 = Disable Closed Captioning encoding. 1 = Enable Closed Captioning encoding.
Register 49
Register 49 XDSSEL[3:0] Default Value 44 D7 D6 D5 D4 D3 D2 CCSEL[3:0] D1 D0
XDSSEL[3:0]
Line Position of Extended Data Services Content Controls which line Extended Data Services data is encoded. Each line enable is independent. 0 = Enable line. 1 = Disable line.
Closed Captioning Line (525-line) 282 283 284 285 Closed Captioning Line (625-line) 333 334 335 336
Bit XDSSEL[0] XDSSEL[1] XDSSEL[2] XDSSEL[3] CCSEL[3:0]3
Line Position of Closed Captioning Content Controls which line Closed Captioning data is encoded. Each line enable is independent. 0 = Enable line. 1 = Disable line.
Bit CCSEL[0] CCSEL[1] CCSEL[2] CCSEL[3] Closed Captioning Line (525-line) 19 20 21 22 Closed Captioning Line (625-line) 21 22 23 24
D860DSA
Conexant
5-33
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 4A-4C
Register 4A 4B 4C Default Value -- -- -- D7 EWSSF2 D6 EWSSF1 D5 D4 SQUARE WSDAT[12:5] WSDAT[20:13] D3 D2 WSDAT[4:1] D1 D0
Reserved
Reserved bits should be set to zero when written and will return zero when read.
EWSSF2
Enable CGMS Function on Field 2 0 = Disable field 2 data. 1 = Enable field 2 data (525 line mode only).
EWSSF1
Enable WSS or CGMS Function on Field 1 0 = Disable field 1 data. 1 = Enable field 1 data.
SQUARE
Square Pixel or CCIR Timing Select for Teletext and WSS 0 = ITU-R BT.601 operation for Teletex and WSS. 1 = Square pixel operation for Teletex and WSS.
WSDAT[20:1]
WSS and CGMS Data Bits
Register 4D-4E
Register 4D 4E Default Value 39 01 D7 D6 D5 D4 TTXHS[7:0] D3 D2 D1 D0
Reserved
TTXHS[10:8]
Reserved bits should be set to zero when written and will return zero when read.
TTXHS[10:0]
TTXREQ Rising Edge Number of clocks from falling edge of HSYNC* to rising edge of TTXREQ minus an offset. Used when TXRM = 0.
TTXHS = (desired distance in clocks) - 2 (3 for slave mode)
5-34
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 4F-50
Register 4F 50 Default Value 07 00 D7 D6 D5 D4 TTXHE[7:0] D3 D2 D1 D0
Reserved
TTXHE[10:8]
Reserved bits should be set to zero when written and will return zero when read.
TTXHE[10:0]
TTXREQ Falling Edge Number of clocks from falling edge of HSYNC* to falling edge of TTXREQ minus an offset. Used when TXRM = 0.
TTXHE = (desired distance in clocks) - 2 (3 for slave mode)
Register 51-52
Register 51 52 Default Value 00 00 D7 D6 D5 D4 TTXBF1[7:0] D3 D2 D1 D0
Reserved
TTXBF1[8]
Reserved bits should be set to zero when written and will return zero when read.
TTXBF1[8:0]
Teletext Start Line for Field 1 Line number of first line of Teletext data for field 1(1).
Register 53-54
Register 53 54 Default Value 00 00 D7 D6 D5 D4 TTXEF1[7:0] D3 D2 D1 D0
Reserved
TTXEF1[8]
Reserved bits should be set to zero when written and will return zero when read.
TTXEF1[8:0]
Teletext End Line for Field 1 Line number of last line of Teletex data for field 1(1).
D860DSA
Conexant
5-35
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 55-56
Register 55 56 Default Value 00 00 D7 D6 D5 D4 TTXBF2[7:0] D3 D2 D1 D0
Reserved
TTXBF2[8]
Reserved bits should be set to zero when written and will return zero when read.
TTXBF2[8:0]
Teletext Start Line for Field 2 Line number of first line of Teletex data for field 2, counted from top of field 2(1).
(TTXBF2 + 313 = PAL/SECAM line)
Register 57-58
Register 57 58 Default Value 00 00 D7 D6 D5 D4 TTXEF2[7:0] D3 D2 D1 D0
Reserved
TTXEF2[8]
Reserved bits should be set to zero when written and will return zero when read.
TTXEF2[8:0]
Teletext End Line for Field 2 Line number of last line of Teletex data for field 2, counted from top of field 2(1).
(TTXEF2 + 313 = PAL/SECAM line)
Register 59
Register 59 Default Value 02 D7 D6 D5 D4 D3 D2 D1 TXRM D0 TXE
Reserved
Reserved bits should be set to zero when written and will return zero when read.
TXRM
TTXREQ Configuration 0 = TTXREQ pin generates request signal based on TTXHS and TTXHE. 1 = TTXREQ pin generates a clock to latch data on TTXDAT pin.
TXE
Teletext Enable 0 = Disable Teletex encoding.
1 = Enable Teletex encoding.
5-36
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Register 5A-5B
Register 5A 5B Default Value 00 00 D7 D6 D5 D4 D3 D2 D1 D0
TTX_DIS[7:0] TTX_DIS[15:8]
Reserved bits should be set to zero when written and will return zero when read.
TTX_DIS[15:0]
Teletext Disable by Line A 1 in these bits disables individual lines of Teletex encoding.
TTX Line (F1 / F2) 8 / 321 9 / 322 10 / 323 11 / 324 12 / 325 13 / 326 14 / 327 15 / 328 TTX Line (F1 / F2) 16 / 329 17 / 330 18 / 331 19 / 332 20 / 333 21 / 334 22 / 335 23 / 336
Bit TTX_DIS[0] TTX_DIS[1] TTX_DIS[2] TTX_DIS[3] TTX_DIS[4] TTX_DIS[5] TTX_DIS[6] TTX_DIS[7]
Bit TTX_DIS[8] TTX_DIS[9] TTX_DIS[10] TTX_DIS[11] TTX_DIS[12] TTX_DIS[13] TTX_DIS[14] TTX_DIS[15]
Register 5C-5F
Register 5C 5D 5E 5F Default Value 7F 00 00 7F D7 D6 D5 D4 D3 D2 D1 D0
MULT_UU[7:0] MULT_VU[7:0] MULT_UV[7:0] MULT_VV[7:0]
MULT_UU[7:0] MULT_VU[7:0] MULT_UV[7:0] MULT_VV[7:0]
Chrominance Matrix Multiplier Chrominance Matrix Multiplier Chrominance Matrix Multiplier Chrominance Matrix Multiplier To rotate the hue by an angle , program the matrix multipliers as follows (except that the value of +128 should be made +127). All register are twos complement. MULT_UU MULT_VU MULT_UV MULT_VV = = = = 128 x Cos() 128 x Sin() 128 x Sin() 128 x Cos()
D860DSA
Conexant
5-37
5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 70-71
Register 70 71 Default Value 80 01 D7 D6 D5 D4 D3 D2 D1 D0
LC_FIFOWIN[7:0] Reserved
LC_FIFOWIN[8]
Reserved bits should be set to zero when written and will return zero when read.
LC_FIFOWIN[8:0]
FIFO Window Defines the number of FIFO locations used to accommodate VID port input.
Register 72
Register 72 Default Value 80 D7 D6 D5 D4 D3 D2 D1 D0
LC_MAXOFF[7:0]
LC_MAXOFF[7:0]
Max Adjustment Defines the maximum internal PLL adjustment applied when locking is enabled.
Register 73
Register 73 XL_GAIN[3:0] Default Value 72 D7 D6 D5 D4 D3 D2 XL_SAT[3:0] D1 D0
XL_GAIN[3:0]
Accelerated Locking Gain Defines the gain applied to the detected frequency error to calculate the internal PLL adjustment for accelerated locking.
XL_SAT[3:0]
Accelerated Locking Saturation Defines the saturation limit applied to the initial internal PLL adjustment of the accelerated locking sequence when XL_SATEN is set.
5-38
Conexant
D860DSA
6
6.0 Parametric Data and Specifications
6.1 Electrical Specifications
6.1.1 Electrical Parameters
Table 6-1. Absolute Maximum Ratings
Parameter
VAA, VDD (measured to GND) Voltage on Any Signal Pin(1) Analog Output Short Circuit Duration to Any Power Supply or Common Storage Temperature Junction Temperature Vapor Phase Soldering (1 Minute)
NOTE(S):
(1)
Symbol
-- -- ISC TS TJ TVSOL
Min(2)
-- GND - 0.5 -- -65 -- --
Typ
-- -- Indefinite -- -- --
Max(2)
7.0 VDD + 0.5 -- +150 +125 220
Units
V V -- C C C
This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply or ground voltage by more than 0.5 V can cause destructive latchup. (2) Stresses beyond limits listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D860DSA
Conexant
6-1
6.0 Parametric Data and Specifications
6.1 Electrical Specifications
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 6-2. DC Characteristics
Parameter
Output Current-DAC Code 1023 (IOUT Full Scale) Output Voltage-DAC Code 1023 Video Level Error (Nominal Resistors) DAC Output Capacitance
Min
-- -- -- --
Typ
34.13 1.28 -- 22
Max
-- -- 5 --
Units
mA V % pF
Digital Inputs (Except SID, SIC)
Input High Voltage Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 2.4 V) 2.0 GND - 0.5 -- -- -- -- -- -- -- 7 VDD + 0.5 0.8 1 -1 -- V V A A pF
SID, SIC
Input High Voltage Input Low Voltage 2.4 -0.5 -- -- 5.25 0.8 V V
Digital Outputs
Output High Voltage (IOH = -400 A) Output Low Voltage (IOL = 3.2 mA) Three-State Current Output Capacitance 2.4 GND -- -- -- -- -- 10 VDD 0.4 50 -- V V A pF
Recommended Operating Conditions
Power Supply (VAA,VDD) Ambient Operating Temperature (TA) DAC Output Load (RL) Nominal RSET (RSET) Thermal Resistance of Package (JA)
NOTE(S):
3.00 0 -- -- --
3.30 -- 37.5 300 43
3.60 70 -- -- --
V C C/W
As the above parameters are guaranteed over the full temperature range (0 C to 70 C), temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 3.3 V.
6-2
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Figure 6-1. Pixel and Control Data Timing Diagram
6.0 Parametric Data and Specifications
6.1 Electrical Specifications
System Clock
t1 t3
Input Timing
HSYNC* VSYNC* BLANK* OSD[7:0] P[7:0] HSYNC* VSYNC* FIELD
t2 t4 t5
Output Timing
861_038
Table 6-3. AC Characteristics
Parameter
CLKIN Frequency(1) CLKIN Pulse Width Duty Cycle Pixel/Control Setup Time Pixel/Control Hold Time Control Output Delay Time Control Output Hold Time t1 t2 t3 t4 t5
Conditions
Minimum
-- 40 3 0 -- 2
Typical
27 50 -- -- -- --
Maximum
-- 60 12 -- 15 --
Units
MHz % ns ns ns ns
Power Characteristics
Total current VAA Supply Current VDD Supply Current Sleep Current 6 DACs enabled 6 DACs enabled -- Using CLKIN as source, PLL and crystal circuitry disabled RSET = 300 , Rload = 37.5 -- -- -- -- -- -- 350 250 100 4 -- -- -- -- mA mA mA mA
DAC Current
--
34.13
--
mA
PLL Current Crystal Circuitry Current
NOTE(S):
(1)
-- --
12 2
-- --
mA mA
The target frequency is 27 MHz for ITU-R BT.601 timing, 24.5454 MHz for 525 line square pixel timing and 29.5 MHz for 625 line square pixel timing.
D860DSA
Conexant
6-3
6.0 Parametric Data and Specifications
6.1 Electrical Specifications
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Table 6-4. Video Quality Specifications
Parameter
Differential Phase Differential Gain Chrominance Nonlinear Gain Chrominance Nonlinear Phase Chroma/Luma Intermodulations Luminance Nonlinearity Chroma/Luma gain inequality Chroma/Luma Delay inequality SNR SNR SNR Chroma AM Chroma PM Frequency Response(1)(2) -- -- -- -- -- Color Saturation Accuracy Hue Accuracy DAC to DAC matching
NOTE(S):
(1) (2)
Conditions
NTC-7 Composite NTC-7 Composite NTC-7 Combination, Referenced to 40 IRE NTC-7 Combination, Referenced to 40 IRE NTC-7 Combination, Referenced to 40 IRE 10 step Luminance Staircase NTC-7 Composite NTC-7 Composite Luminance Ramp, tilt null engaged 50 IRE Pedestal 50 IRE Pedestal Red Field Red Field 0.5 MHz Packet, Multiburst 1 MHz Packet, Multiburst 2 MHz Packet, Multiburst 3 MHz Packet, Multiburst 3.58 MHz Packet, Multiburst 4.2 MHz Packet, Multiburst -- -- --
Min
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typical
2.3 0.67 1.75 0.1 0.2 1.1 0.3 0.9 -61.5 -73 -78.5 -65 -65 -0.67 -0.71 -0.83 -0.94 -1.07 -1.23 1 1 --
Max
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5
Units
deg p-p % p-p +/- % +/- deg +/- % +/- % +/- % ns dB RMS dB RMS dB p-p dB dB dB dB dB dB dB dB IRE deg %
Internal peaking and reduction filters not engaged. Without external reconstruction filter. 3. Temperature range tested: 0 C to 70 C. 4. Power supply voltage tested: 2.7 V to 3.6 V.
6-4
Conexant
D860DSA
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
6.0 Parametric Data and Specifications
6.2 Mechanical Drawing
6.2 Mechanical Drawing
Figure 6-2. 80 MQFP Package Diagram
80 MQFP - 1.6/0.15mm FORM
TOP VIEW
D D2
BOTTOM VIEW
D1
E2 e b
E
E1
SIDE VIEW
A
S Y M B O L
ALL DIMENSIONS IN MILLIMETERS
DETAIL A
A A1 A2 D
MIN. --0.05 16.95
NOM. ----2.0 REF. --14.0 REF. 12.35 REF.
MAX. 2.4 0.35 17.45
A2
D1 D2 E E1 E2 L L1 e b 0.25 0.73 16.95
--14.0 REF. 12.35 REF. 0.80 16 REF. 0.65 BSC ---
17.45
A1
L
1.60 (.063) REF.
1.03
0.45
861_041
D860DSA
Conexant
6-5
6.0 Parametric Data and Specifications
6.2 Mechanical Drawing
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
6-6
Conexant
D860DSA
0.0 Sales Offices
Further Information literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com Hong Kong Phone: (852) 2827 0181 Fax: (852) 2827 6488 India Phone: (91 11) 692 4780 Fax: (91 11) 692 4712 Korea Phone: (82 2) 565 2880 Fax: (82 2) 565 1440 Phone: (82 53) 745 2880 Fax: (82 53) 745 1440
World Headquarters
Conexant Systems, Inc. 4311 Jamboree Road P. O. Box C Newport Beach, CA 92658-8902 Phone: (949) 483-4600 Fax: (949) 483-6375 U.S. Florida/South America Phone: (727) 799-8406 Fax: (727) 799-8306 U.S. Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 U.S. Mid-Atlantic Phone: (215) 244-6784 Fax: (215) 244-9292 U.S. North Central Phone: (630) 773-3454 Fax: (630) 773-3907 U.S. Northeast Phone: (978) 692-7660 Fax: (978) 692-8185 U.S. Northwest/Pacific West Phone: (408) 249-9696 Fax: (408) 249-7113 U.S. South Central Phone: (972) 733-0723 Fax: (972) 407-0639 U.S. Southeast Phone: (919) 858-9110 Fax: (919) 858-8669 U.S. Southwest Phone: (949) 483-9119 Fax: (949) 483-9090
Europe Headquarters
Conexant Systems France Les Taissounieres B1 1681 Route des Dolines BP 283 06905 Sophia Antipolis Cedex FRANCE Phone: (33 4) 93 00 33 35 Fax: (33 4) 93 00 33 03 Europe Central Phone: (49 89) 829 1320 Fax: (49 89) 834 2734 Europe Mediterranean Phone: (39 02) 9317 9911 Fax: (39 02) 9317 9913 Europe North Phone: (44 1344) 486 444 Fax: (44 1344) 486 555 Europe South Phone: (33 1) 41 44 36 50 Fax: (33 1) 41 44 36 90
Middle East Headquarters
Conexant Systems Commercial (Israel) Ltd. P. O. Box 12660 Herzlia 46733, ISRAEL Phone: (972 9) 952 4064 Fax: (972 9) 951 3924
Japan Headquarters
Conexant Systems Japan Co., Ltd. Shimomoto Building 1-46-3 Hatsudai, Shibuya-ku, Tokyo 151-0061 JAPAN Phone: (81 3) 5371-1567 Fax: (81 3) 5371-1501
APAC Headquarters
Conexant Systems Singapore, Pte. Ltd. 1 Kim Seng Promenade Great World City #09-01 East Tower SINGAPORE 237994 Phone: (65) 737 7355 Fax: (65) 737 9077 Australia Phone: (61 2) 9869 4088 Fax: (61 2) 9869 4077 China Phone: (86 2) 6361 2515 Fax: (86 2) 6361 2516
Taiwan Headquarters
Conexant Systems, Taiwan Co., Ltd. Room 2808 International Trade Building 333 Keelung Road, Section 1 Taipei 110, TAIWAN, ROC Phone: (886 2) 2720 0282 Fax: (886 2) 2757 6760

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